Searched refs:ubwc_config (Results 1 – 5 of 5) sorted by relevance
433 if (!adreno_gpu->ubwc_config) in adreno_get_param()435 *value = adreno_gpu->ubwc_config->highest_bank_bit; in adreno_get_param()441 if (!adreno_gpu->ubwc_config) in adreno_get_param()443 *value = qcom_ubwc_swizzle(adreno_gpu->ubwc_config); in adreno_get_param()446 if (!adreno_gpu->ubwc_config) in adreno_get_param()448 *value = qcom_ubwc_macrotile_mode(adreno_gpu->ubwc_config); in adreno_get_param()
834 BUG_ON(adreno_gpu->ubwc_config->highest_bank_bit < 13); in a5xx_hw_init()835 hbb = adreno_gpu->ubwc_config->highest_bank_bit - 13; in a5xx_hw_init()1770 adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); in a5xx_gpu_init()1771 if (IS_ERR(adreno_gpu->ubwc_config)) in a5xx_gpu_init()1772 return ERR_CAST(adreno_gpu->ubwc_config); in a5xx_gpu_init()
239 const struct qcom_ubwc_cfg_data *ubwc_config; member
751 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; in a6xx_set_ubwc_config()2782 adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); in a6xx_gpu_init()2783 if (IS_ERR(adreno_gpu->ubwc_config)) { in a6xx_gpu_init()2784 ret = PTR_ERR(adreno_gpu->ubwc_config); in a6xx_gpu_init()
277 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; in a8xx_set_ubwc_config()