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Searched refs:uartclk (Results 1 – 25 of 115) sorted by relevance

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/linux/drivers/tty/serial/8250/
H A D8250_ni.c70 u32 uartclk; member
331 uart->port.uartclk = info->uartclk; in ni16550_probe()
337 if (!uart->port.uartclk) { in ni16550_probe()
340 uart->port.uartclk = clk_get_rate(data->clk); in ni16550_probe()
343 if (!uart->port.uartclk) in ni16550_probe()
404 .uartclk = 33333333,
409 .uartclk = 1843200,
416 .uartclk = 22222222,
423 .uartclk = 29629629,
H A D8250_acorn.c27 unsigned int uartclk; member
65 uart.port.uartclk = type->uartclk; in serial_card_probe()
96 .uartclk = 7372800,
103 .uartclk = 3686400,
H A D8250_hp300.c116 port.uartclk = HPAPCI_BAUD_BASE * 16; in hp300_setup_serial_console()
133 port.uartclk = HPDCA_BAUD_BASE * 16; in hp300_setup_serial_console()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
257 uart.port.uartclk = HPAPCI_BAUD_BASE * 16; in hp300_8250_init()
H A D8250_ingenic.c86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
107 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud); in ingenic_earlycon_setup_tail()
147 if (dev->port.uartclk >= 16000000) in jz4750_early_console_setup()
148 dev->port.uartclk /= 2; in jz4750_early_console_setup()
298 uart.port.uartclk = clk_get_rate(data->clk_baud); in ingenic_uart_probe()
H A D8250_loongson.c90 quot = DIV_ROUND_CLOSEST((port->uartclk << 4), baud); in loongson_frac_get_divisor()
147 if (!port->uartclk) { in loongson_uart_probe()
152 port->uartclk = clk_get_rate(priv->clk); in loongson_uart_probe()
H A D8250_omap.c242 unsigned int uartclk = port->uartclk; in omap_8250_get_divisor() local
246 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); in omap_8250_get_divisor()
247 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); in omap_8250_get_divisor()
254 abs_d13 = abs(baud - uartclk / 13 / div_13); in omap_8250_get_divisor()
255 abs_d16 = abs(baud - uartclk / 16 / div_16); in omap_8250_get_divisor()
513 port->uartclk / 16 / UART_DIV_MAX, in omap_8250_set_termios()
514 port->uartclk / 13); in omap_8250_set_termios()
844 baud = port->uartclk / (16 * priv->quot); in omap8250_rs485_config()
846 baud = port->uartclk / (1 in omap8250_rs485_config()
[all...]
/linux/arch/arm/mach-omap1/
H A Dserial.c73 .uartclk = OMAP16XX_BASE_BAUD * 16,
81 .uartclk = OMAP16XX_BASE_BAUD * 16,
89 .uartclk = OMAP16XX_BASE_BAUD * 16,
112 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; in omap_serial_init()
113 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; in omap_serial_init()
114 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; in omap_serial_init()
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi56 clock-names = "uartclk", "apb_pclk";
65 clock-names = "uartclk", "apb_pclk";
74 clock-names = "uartclk", "apb_pclk";
83 clock-names = "uartclk", "apb_pclk";
92 clock-names = "uartclk", "apb_pclk";
/linux/arch/mips/ath25/
H A Ddevices.c74 void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk) in ath25_serial_setup() argument
86 s.uartclk = uartclk; in ath25_serial_setup()
/linux/arch/mips/mti-malta/
H A Dmalta-platform.c34 .uartclk = 1843200, \
49 .uartclk = 3686400, /* Twice the usual clk! */
/linux/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts73 uartclk: clock-14745600 { label
249 clocks = <&uartclk>, <&pclk>;
250 clock-names = "uartclk", "apb_pclk";
255 clocks = <&uartclk>, <&pclk>;
256 clock-names = "uartclk", "apb_pclk";
279 clocks = <&uartclk>, <&pclk>;
H A Dintegratorap.dts67 uartclk: clock-14745600 { label
216 clocks = <&uartclk>, <&pclk>;
217 clock-names = "uartclk", "apb_pclk";
223 clocks = <&uartclk>, <&pclk>;
224 clock-names = "uartclk", "apb_pclk";
/linux/arch/arm/mach-footbridge/
H A Disa.c52 .uartclk = 1843200,
60 .uartclk = 1843200,
/linux/arch/mips/loongson2ef/common/
H A Dserial.c25 .uartclk = clk, \
34 .uartclk = clk, \
/linux/drivers/tty/serial/
H A D21285.c244 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); in serial21285_set_termios()
246 b = port->uartclk / (16 * quot); in serial21285_set_termios()
347 if (ser->baud_base != port->uartclk / 16) in serial21285_verify_port()
381 serial21285_port.uartclk = mem_fclk_21285 / 4; in serial21285_setup_ports()
431 *baud = port->uartclk / (16 * (tmp + 1)); in serial21285_get_options()
H A Dsccnxp.c310 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud); in sccnxp_set_baud()
312 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std); in sccnxp_set_baud()
326 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); in sccnxp_set_baud()
887 int i, ret, uartclk; in sccnxp_probe() local
923 uartclk = 0; in sccnxp_probe()
925 uartclk = clk_get_rate(clk); in sccnxp_probe()
928 if (!uartclk) { in sccnxp_probe()
930 uartclk = s->chip->freq_std; in sccnxp_probe()
934 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { in sccnxp_probe()
989 s->port[i].uartclk = uartclk; in sccnxp_probe()
H A Dlpc32xx_hs.c207 static unsigned int __serial_get_clock_div(unsigned long uartclk, in __serial_get_clock_div() argument
214 div = uartclk / rate; in __serial_get_clock_div()
224 comprate = uartclk / ((hsu_rate + 1) * 14); in __serial_get_clock_div()
485 port->uartclk / 14); in serial_lpc32xx_set_termios()
487 quot = __serial_get_clock_div(port->uartclk, baud); in serial_lpc32xx_set_termios()
636 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; in serial_hs_lpc32xx_probe()
H A Daltera_uart.c183 baudclk = port->uartclk / baud; in altera_uart_set_termios()
498 unsigned int baudclk = port->uartclk / dev->baud; in altera_uart_earlycon_setup()
566 port->uartclk = platp->uartclk; in altera_uart_probe()
569 &port->uartclk); in altera_uart_probe()
H A Dmax310x.c528 div = port->uartclk / baud; in max310x_set_baud()
547 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
556 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
1035 port->uartclk / 16 / 0xffff, in max310x_set_termios()
1036 port->uartclk / 4); in max310x_set_termios()
1315 unsigned int uartclk = 0; in max310x_probe() local
1328 device_property_read_u32(dev, "clock-frequency", &uartclk); in max310x_probe()
1344 freq = uartclk; in max310x_probe()
1396 ret = max310x_set_ref_clk(dev, s, freq, &uartclk, xtal); in max310x_probe()
1400 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); in max310x_probe()
[all …]
H A Dst-asc.c479 port->uartclk = clk_get_rate(ascport->clk); in asc_set_termios()
481 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); in asc_set_termios()
532 asc_out(port, ASC_BAUDRATE, (port->uartclk / (16 * baud))); in asc_set_termios()
545 do_div(dividend, port->uartclk / 16); in asc_set_termios()
717 ascport->port.uartclk = clk_get_rate(ascport->clk); in asc_init_port()
718 WARN_ON(ascport->port.uartclk == 0); in asc_init_port()
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8.dtsi204 clock-names = "uartclk", "apb_pclk";
212 clock-names = "uartclk", "apb_pclk";
220 clock-names = "uartclk", "apb_pclk";
228 clock-names = "uartclk", "apb_pclk";
H A Drtsm_ve-motherboard.dtsi174 clock-names = "uartclk", "apb_pclk";
182 clock-names = "uartclk", "apb_pclk";
190 clock-names = "uartclk", "apb_pclk";
198 clock-names = "uartclk", "apb_pclk";
/linux/arch/mips/bcm47xx/
H A Dserial.c44 p->uartclk = ssb_port->baud_base; in uart8250_init_ssb()
70 p->uartclk = bcma_port->baud_base; in uart8250_init_bcma()
/linux/arch/sh/boards/mach-se/7343/
H A Dsetup.c78 .uartclk = 7372800,
85 .uartclk = 7372800,
/linux/arch/mips/alchemy/common/
H A Dplatform.c103 long uartclk; in alchemy_setup_uarts() local
115 uartclk = clk_get_rate(clk); in alchemy_setup_uarts()
128 ports[s].uartclk = uartclk; in alchemy_setup_uarts()

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