Home
last modified time | relevance | path

Searched refs:train_set (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c110 u8 *train_set = dp->link.train_set; in hibmc_dp_link_training_cr_pre() local
123 train_set[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; in hibmc_dp_link_training_cr_pre()
125 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr_pre()
129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
141 u8 train_set[HIBMC_DP_LANE_NUM_MAX] = {0}; in hibmc_dp_link_get_adjust_train() local
145 train_set[lane] = drm_dp_get_adjust_request_voltage(lane_status, lane) | in hibmc_dp_link_get_adjust_train()
148 if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) { in hibmc_dp_link_get_adjust_train()
149 memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX); in hibmc_dp_link_get_adjust_train()
235 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr()
239 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
[all …]
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c332 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
407 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
697 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
711 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
726 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set) in zynqmp_dp_update_vs_emph() argument
731 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, in zynqmp_dp_update_vs_emph()
739 u8 train = train_set[i]; in zynqmp_dp_update_vs_emph()
783 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); in zynqmp_dp_link_train_cr()
797 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
802 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h1826 u8 train_set[4]; member