| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 181 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info, in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
194 tiling_info->gfxversion = DcGfxVersion8; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
196 tiling_info->gfx8.num_banks = num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
197 tiling_info->gfx8.array_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
201 tiling_info->gfx8.bank_height = bankh; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
202 tiling_info->gfx8.tile_aspect = mtaspect; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
203 tiling_info->gfx8.tile_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
207 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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| H A D | amdgpu_dm_plane.h | 50 struct dc_tiling_info *tiling_info,
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| H A D | amdgpu_dm.c | 6174 &plane_info->tiling_info, in fill_dc_plane_info_and_addr()
6223 dc_plane_state->tiling_info = plane_info.tiling_info; in fill_dc_plane_attributes()
8002 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
8005 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; in dm_validate_stream_and_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_mem_input.c | 101 struct dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 struct dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
653 struct dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
662 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
673 struct dc_tiling_info *tiling_info, in dce60_mi_program_surface_config() argument
682 program_tiling(dce_mi, tiling_info); in dce60_mi_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_mem_input_v.c | 526 struct dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
544 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
566 struct dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
570 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
571 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
639 struct dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
648 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 45 struct dc_tiling_info *tiling_info, in hubp201_program_surface_config() argument
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 2747 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; in get_plane_info_update_type()
2749 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { in get_plane_info_update_type()
3128 surface->tiling_info = in copy_surface_update_to_plane()
3129 srf_update->plane_info->tiling_info; in copy_surface_update_to_plane()
6616 if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) { in dc_capture_register_software_state()
6618 state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle; in dc_capture_register_software_state()
6619 state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes; in dc_capture_register_software_state()
6620 state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks; in dc_capture_register_software_state()
6621 state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave; in dc_capture_register_software_state()
6622 state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines; in dc_capture_register_software_state()
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| H A D | dc_hw_sequencer.c | 2026 struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info; in hwss_program_surface_config() local
2036 tiling_info, in hwss_program_surface_config()
2066 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
3878 struct dc_tiling_info *tiling_info, in hwss_add_hubp_program_surface_config() argument
3889 …state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info; in hwss_add_hubp_program_surface_config()
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| H A D | dc_resource.c | 4437 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| /linux/include/uapi/drm/ |
| H A D | amdgpu_drm.h | 714 __u64 tiling_info; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 164 struct dc_tiling_info *tiling_info; member
1931 struct dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 404 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 1452 struct dc_tiling_info tiling_info; member
1525 struct dc_tiling_info tiling_info; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 1849 &plane_state->tiling_info, in dcn20_update_dchubp_dpp()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3719 plane_state->format, &plane_state->tiling_info, size, in dcn401_update_dchubp_dpp_sequence()
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