| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 179 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
193 tiling_info->gfx8.num_banks = num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
194 tiling_info->gfx8.array_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
196 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
197 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
198 tiling_info->gfx8.bank_height = bankh; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.tile_aspect = mtaspect; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.tile_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
204 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
207 tiling_info->gfx8.pipe_config = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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| H A D | amdgpu_dm_plane.h | 50 union dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_mem_input.c | 101 union dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 union dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
633 union dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
642 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
653 union dc_tiling_info *tiling_info, in dce60_mi_program_surface_config() argument
662 program_tiling(dce_mi, tiling_info); in dce60_mi_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | mem_input.h | 153 union dc_tiling_info *tiling_info,
167 union dc_tiling_info *tiling_info,
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| H A D | hubp.h | 168 union dc_tiling_info *tiling_info,
182 union dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 45 union dc_tiling_info *tiling_info, in hubp201_program_surface_config() argument
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/ |
| H A D | dcn35_hubp.c | 175 union dc_tiling_info *tiling_info, in hubp35_program_surface_config() argument
185 hubp3_program_tiling(hubp2, tiling_info, format); in hubp35_program_surface_config()
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| H A D | dcn35_hubp.h | 68 union dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
319 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
331 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| H A D | dcn30_hubp.c | 398 union dc_tiling_info *tiling_info, in hubp3_program_surface_config() argument
408 hubp3_program_tiling(hubp2, tiling_info, format); in hubp3_program_surface_config()
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| H A D | dcn30_hubp.h | 267 union dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_utils.c | 403 memcpy(&phantom_plane->tiling_info, &main_plane->tiling_info, in dml21_add_phantom_plane()
404 sizeof(phantom_plane->tiling_info)); in dml21_add_phantom_plane()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_mall_phantom.c | 765 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, in enable_phantom_plane()
766 sizeof(phantom_plane->tiling_info)); in enable_phantom_plane()
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| H A D | dml2_translation_helper.c | 885 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()
889 switch (in->tiling_info.gfx_addr3.swizzle) { in populate_dml_surface_cfg_from_plane_state()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gem.c | 606 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
616 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.c | 571 union dc_tiling_info *tiling_info, in hubp401_program_surface_config() argument
581 hubp401_program_tiling(hubp2, tiling_info, format); in hubp401_program_surface_config()
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| H A D | dcn401_hubp.h | 305 union dc_tiling_info *tiling_info,
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.h | 385 union dc_tiling_info *tiling_info,
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| H A D | dcn20_hubp.c | 539 union dc_tiling_info *tiling_info, in hubp2_program_surface_config() argument
549 hubp2_program_tiling(hubp2, tiling_info, format); in hubp2_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 538 union dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
546 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
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| H A D | dcn10_hubp.h | 709 union dc_tiling_info *tiling_info,
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| /linux/include/uapi/drm/ |
| H A D | amdgpu_drm.h | 441 __u64 tiling_info; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1010 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 404 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 2216 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
2925 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
2937 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
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