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Searched refs:tiling_flags (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_object.c529 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
545 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
583 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
605 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
613 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
614 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
615 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
616 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
617 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
658 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
[all …]
H A Dradeon_fbdev.c64 u32 tiling_flags = 0; in radeon_fbdev_create_pinned_object() local
90 tiling_flags = RADEON_TILING_MACRO; in radeon_fbdev_create_pinned_object()
95 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeon_fbdev_create_pinned_object()
98 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeon_fbdev_create_pinned_object()
105 if (tiling_flags) { in radeon_fbdev_create_pinned_object()
107 tiling_flags | RADEON_TILING_SURFACE, in radeon_fbdev_create_pinned_object()
H A Dr300.c719 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
721 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
723 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
788 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
790 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
792 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
873 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
875 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
877 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
H A Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
H A Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
H A Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
H A Datombios_crtc.c1145 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1265 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1339 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1577 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1579 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1582 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
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H A Dr100.c1312 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1314 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1654 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1656 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1735 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1737 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3112 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3119 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3122 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3125 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
H A Dr600_cs.c1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
H A Dradeon_gem.c568 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
589 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
H A Dradeon_vm.c146 list[0].tiling_flags = 0; in radeon_vm_get_bos()
157 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
H A Dradeon_display.c491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
H A Devergreen.c1111 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1115 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1116 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields()
1117 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields()
1118 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
H A Dr600.c3029 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_display.c204 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
260 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
730 int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE); in convert_tiling_flags_to_modifier_gfx12()
736 AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in convert_tiling_flags_to_modifier_gfx12()
761 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
764 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
773 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
859 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
866 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
891 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
[all …]
H A Damdgpu_object.c1115 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1122 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1126 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1138 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1146 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1147 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
H A Ddce_v8_0.c1797 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1835 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1838 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1920 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1923 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1924 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1925 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1926 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1927 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1936 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
H A Ddce_v6_0.c1888 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1925 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
2008 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
2011 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
2012 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
2013 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
2014 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
2015 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
2023 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
2027 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
H A Ddce_v10_0.c1850 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1888 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1891 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1981 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1984 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1985 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1986 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1987 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1988 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2001 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c1900 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1938 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1941 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2031 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2034 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2035 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2036 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2037 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2038 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2051 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c181 uint64_t tiling_flags) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
204 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
210 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
842 const uint64_t tiling_flags, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument
[all …]
H A Damdgpu_dm_plane.h49 const uint64_t tiling_flags,
H A Damdgpu_dm.c5749 const u64 tiling_flags, in fill_dc_plane_info_and_addr() argument
5847 plane_info->rotation, tiling_flags, in fill_dc_plane_info_and_addr()
5883 afb->tiling_flags, in fill_dc_plane_attributes()
9413 afb->tiling_flags, in amdgpu_dm_commit_planes()
11170 if (old_afb->tiling_flags != new_afb->tiling_flags || in should_reset_plane()
11225 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; in dm_check_cursor_fb()
11227 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; in dm_check_cursor_fb()
11229 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && in dm_check_cursor_fb()
11230 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && in dm_check_cursor_fb()
11231 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; in dm_check_cursor_fb()
/linux/include/uapi/drm/
H A Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member