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Searched refs:tiling_flags (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_object.c529 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
545 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
583 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
605 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
613 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
614 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
615 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
616 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
617 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
658 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
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H A Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
H A Dr300.c719 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
721 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
723 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
788 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
790 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
792 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
873 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
875 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
877 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
H A Devergreen_cs.c94 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
96 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
98 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1181 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1183 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1186 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1367 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1368 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
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H A Dr100.c1312 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1314 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1654 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1656 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1735 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1737 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3113 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3120 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3123 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3126 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
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H A Dr600_cs.c1046 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1145 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1148 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1479 u32 tiling_flags) in r600_check_texture_resource() argument
1501 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1503 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1972 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1974 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1990 reloc->tiling_flags); in r600_packet3_check()
H A Dradeon_vm.c145 list[0].tiling_flags = 0; in radeon_vm_get_bos()
156 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
H A Dr600.c3029 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c182 uint64_t tiling_flags) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
185 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
188 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
189 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
190 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
191 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
192 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
205 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
211 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
844 const uint64_t tiling_flags, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument
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H A Damdgpu_dm_plane.h49 const uint64_t tiling_flags,
H A Damdgpu_dm.c6191 const u64 tiling_flags, in fill_dc_plane_info_and_addr() argument
6289 plane_info->rotation, tiling_flags, in fill_dc_plane_info_and_addr()
6325 afb->tiling_flags, in fill_dc_plane_attributes()
10097 afb->tiling_flags, in amdgpu_dm_commit_planes()
11898 if (old_afb->tiling_flags != new_afb->tiling_flags || in should_reset_plane()
11953 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; in dm_check_cursor_fb()
11955 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; in dm_check_cursor_fb()
11957 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && in dm_check_cursor_fb()
11958 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && in dm_check_cursor_fb()
11959 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; in dm_check_cursor_fb()
/linux/include/uapi/drm/
H A Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ttm.c319 uint64_t from, to, cur_size, tiling_flags; in amdgpu_ttm_copy_mem_to_mem() local
347 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags); in amdgpu_ttm_copy_mem_to_mem()
348 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in amdgpu_ttm_copy_mem_to_mem()
349 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); in amdgpu_ttm_copy_mem_to_mem()
350 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); in amdgpu_ttm_copy_mem_to_mem()
352 AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE); in amdgpu_ttm_copy_mem_to_mem()
H A Damdgpu_mode.h303 uint64_t tiling_flags; member