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Searched refs:tiling (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/tegra/
H A Dfb.c38 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
44 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA; in tegra_fb_get_tiling()
46 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU; in tegra_fb_get_tiling()
53 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
54 tiling->value = 0; in tegra_fb_get_tiling()
58 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
59 tiling->value = 0; in tegra_fb_get_tiling()
63 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
64 tiling->value = 0; in tegra_fb_get_tiling()
68 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
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H A Dhub.c433 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
447 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_shared_plane_atomic_check()
451 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
457 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && in tegra_shared_plane_atomic_check()
637 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) in tegra_shared_plane_atomic_update()
717 unsigned long height = tegra_plane_state->tiling.value; in tegra_shared_plane_atomic_update()
720 switch (tegra_plane_state->tiling.mode) { in tegra_shared_plane_atomic_update()
H A Dplane.h49 struct tegra_bo_tiling tiling; member
H A Dplane.c63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
H A Ddc.c429 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
431 switch (window->tiling.mode) { in tegra_dc_setup_window()
448 switch (window->tiling.mode) { in tegra_dc_setup_window()
628 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
660 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
664 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
760 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
H A Ddrm.h186 struct tegra_bo_tiling *tiling);
H A Ddrm.c651 bo->tiling.mode = mode; in tegra_gem_set_tiling()
652 bo->tiling.value = value; in tegra_gem_set_tiling()
673 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
686 args->value = bo->tiling.value; in tegra_gem_get_tiling()
H A Ddc.h155 struct tegra_bo_tiling tiling; member
H A Dgem.c419 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c99 enum client_tiling tiling; member
137 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) in fast_blit_ok()
171 if (src->tiling == CLIENT_TILING_Y) { in prepare_blit()
175 } else if (src->tiling == CLIENT_TILING_X) { in prepare_blit()
182 if (dst->tiling == CLIENT_TILING_Y) { in prepare_blit()
186 } else if (dst->tiling == CLIENT_TILING_X) { in prepare_blit()
208 if (src->tiling == CLIENT_TILING_Y) in prepare_blit()
210 if (dst->tiling == CLIENT_TILING_Y) in prepare_blit()
228 if (src->tiling) { in prepare_blit()
234 if (dst->tiling) { in prepare_blit()
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H A Di915_gem_mman.c37 unsigned int tiling; member
50 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
56 if (tile->tiling == I915_TILING_X) { in tiled_offset()
110 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
113 tile->tiling, tile->stride, err); in check_partial_mapping()
117 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
168 tile->tiling ? tile_row_pages(obj) : 0, in check_partial_mapping()
169 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride, in check_partial_mapping()
198 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mappings()
201 tile->tiling, tile->stride, err); in check_partial_mappings()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c79 if (fence->tiling) { in i965_write_fence_reg()
88 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
120 if (fence->tiling) { in i915_write_fence_reg()
122 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
123 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
154 if (fence->tiling) { in i830_write_fence_reg()
158 if (fence->tiling == I915_TILING_Y) in i830_write_fence_reg()
211 fence->tiling = 0; in fence_update()
230 fence->tiling = i915_gem_object_get_tiling(vma->obj); in fence_update()
307 fence->tiling = 0; in i915_vma_revoke_fence()
H A Dintel_ggtt_fencing.h40 u32 tiling; member
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_tiling.h16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
/linux/drivers/gpu/drm/vc4/
H A Dvc4_plane.c1221 u32 tiling, src_x, src_y; in vc4_plane_mode_set() local
1273 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
1331 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
1366 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
1372 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
1375 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
1378 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
1491 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
1529 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
1751 u32 tiling, src_x, src_y; in vc6_plane_mode_set() local
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c381 surface->tiling = dml2_sw_64kb_2d; in populate_dml21_dummy_surface_cfg()
458 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
461 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c389 int tiling, in dml1_rq_dlg_get_row_heights() argument
394 bool surf_linear = (tiling == dm_sw_linear); in dml1_rq_dlg_get_row_heights()
445 if (tiling != dm_sw_linear) in dml1_rq_dlg_get_row_heights()
/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-reserved.rst239 similitude with ``V4L2_PIX_FMT_MM21`` in term of alignment and tiling.
H A Dpixfmt-yuv-planar.rst383 Semi-planar YUV 4:2:0 formats, using macroblock tiling. The chroma plane is
458 ``V4L2_PIX_FMT_NV15_4L4`` Semi-planar 10-bit YUV 4:2:0 formats, using 4x4 tiling.
/linux/Documentation/gpu/amdgpu/display/
H A Dmpo-overview.rst167 - ``kms_plane_multiple@atomic-pipe-*-tiling-``
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c2748 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; in get_plane_info_update_type() local
2750 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { in get_plane_info_update_type()
2754 switch (tiling->gfxversion) { in get_plane_info_update_type()
2758 if (tiling->gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
2764 if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { in get_plane_info_update_type()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dcom.fuc518 // to correctly handle tiling.
/linux/Documentation/userspace-api/
H A Ddma-buf-alloc-exchange.rst82 pixels at the start of vertically-consecutive tiling blocks. For linear
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c3769 || p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in CalculateSwathAndDETConfiguration()
3813 if (p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in CalculateSwathAndDETConfiguration()
7348 …t_setting_params->is_gfx11 = dml_get_gfx_version(display_cfg->plane_descriptors[k].surface.tiling); in dml_core_ms_prefetch_check()
8059 …if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear && dml_is_vertical_rotation… in dml_core_mode_support()
8067 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_support()
8186 if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in dml_core_mode_support()
8936 s->SurfParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_support()
9366 calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_support()
10555 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_programming()
10727 s->SurfaceParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_programming()
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