| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_tiling.h | 16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.h | 40 u32 tiling; member
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | plane.h | 49 struct tegra_bo_tiling tiling; member
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| H A D | plane.c | 63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
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| H A D | drm.h | 186 struct tegra_bo_tiling *tiling);
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| H A D | drm.c | 651 bo->tiling.mode = mode; in tegra_gem_set_tiling()
652 bo->tiling.value = value; in tegra_gem_set_tiling()
673 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
686 args->value = bo->tiling.value; in tegra_gem_get_tiling()
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| H A D | dc.h | 155 struct tegra_bo_tiling tiling; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | dml1_display_rq_dlg_calc.c | 389 int tiling, in dml1_rq_dlg_get_row_heights() argument
394 bool surf_linear = (tiling == dm_sw_linear); in dml1_rq_dlg_get_row_heights()
445 if (tiling != dm_sw_linear) in dml1_rq_dlg_get_row_heights()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | skl_universal_plane.c | 3060 u32 val, base, offset, stride_mult, tiling, alpha; in skl_get_initial_plane_config() local
3108 tiling = val & PLANE_CTL_TILED_MASK; in skl_get_initial_plane_config()
3109 switch (tiling) { in skl_get_initial_plane_config()
3153 MISSING_CASE(tiling); in skl_get_initial_plane_config()
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| /linux/drivers/staging/media/ipu3/ |
| H A D | ipu3-abi.h | 919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-reserved.rst | 239 similitude with ``V4L2_PIX_FMT_MM21`` in term of alignment and tiling.
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| H A D | pixfmt-yuv-planar.rst | 383 Semi-planar YUV 4:2:0 formats, using macroblock tiling. The chroma plane is
458 ``V4L2_PIX_FMT_NV15_4L4`` Semi-planar 10-bit YUV 4:2:0 formats, using 4x4 tiling.
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| H A D | buffer.rst | 48 pixel format, the line stride, the tiling orientation or the rotation) is
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 167 - ``kms_plane_multiple@atomic-pipe-*-tiling-``
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 2747 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; in get_plane_info_update_type() local
2749 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { in get_plane_info_update_type()
2753 switch (tiling->gfxversion) { in get_plane_info_update_type()
2757 if (tiling->gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
2763 if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { in get_plane_info_update_type()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| H A D | com.fuc | 518 // to correctly handle tiling.
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| /linux/Documentation/userspace-api/ |
| H A D | dma-buf-alloc-exchange.rst | 82 pixels at the start of vertically-consecutive tiling blocks. For linear
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