| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_client_blt.c | 99 enum client_tiling tiling; member
137 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) in fast_blit_ok()
171 if (src->tiling == CLIENT_TILING_Y) { in prepare_blit()
175 } else if (src->tiling == CLIENT_TILING_X) { in prepare_blit()
182 if (dst->tiling == CLIENT_TILING_Y) { in prepare_blit()
186 } else if (dst->tiling == CLIENT_TILING_X) { in prepare_blit()
208 if (src->tiling == CLIENT_TILING_Y) in prepare_blit()
210 if (dst->tiling == CLIENT_TILING_Y) in prepare_blit()
228 if (src->tiling) { in prepare_blit()
234 if (dst->tiling) { in prepare_blit()
[all …]
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| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_tiling.h | 16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | hub.c | 433 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
447 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_shared_plane_atomic_check()
451 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
457 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && in tegra_shared_plane_atomic_check()
637 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) in tegra_shared_plane_atomic_update()
717 unsigned long height = tegra_plane_state->tiling.value; in tegra_shared_plane_atomic_update()
720 switch (tegra_plane_state->tiling.mode) { in tegra_shared_plane_atomic_update()
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| H A D | plane.h | 49 struct tegra_bo_tiling tiling; member
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| H A D | plane.c | 63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
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| H A D | dc.c | 528 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
530 switch (window->tiling.mode) { in tegra_dc_setup_window()
547 switch (window->tiling.mode) { in tegra_dc_setup_window()
727 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
759 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
763 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
859 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.h | 40 u32 tiling; member
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | skl_universal_plane.c | 3063 u32 val, base, offset, stride_mult, tiling, alpha; in skl_get_initial_plane_config() local
3111 tiling = val & PLANE_CTL_TILED_MASK; in skl_get_initial_plane_config()
3112 switch (tiling) { in skl_get_initial_plane_config()
3156 MISSING_CASE(tiling); in skl_get_initial_plane_config()
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| /linux/drivers/staging/media/ipu3/ |
| H A D | ipu3-abi.h | 919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-reserved.rst | 239 similitude with ``V4L2_PIX_FMT_MM21`` in term of alignment and tiling.
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| H A D | pixfmt-yuv-planar.rst | 383 Semi-planar YUV 4:2:0 formats, using macroblock tiling. The chroma plane is
458 ``V4L2_PIX_FMT_NV15_4L4`` Semi-planar 10-bit YUV 4:2:0 formats, using 4x4 tiling.
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| H A D | buffer.rst | 48 pixel format, the line stride, the tiling orientation or the rotation) is
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 167 - ``kms_plane_multiple@atomic-pipe-*-tiling-``
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn5_funcs_mode_programming.c | 171 display_cfg->plane_descriptors[k].surface.tiling, in dcn5_mode_programming()
324 s->SurfaceParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling; in dcn5_mode_programming()
1053 display_cfg->plane_descriptors[k].surface.tiling, in dcn5_mode_programming()
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| H A D | dml2_core_dcn5_calcs_dchub.c | 770 || dml2_core_utils_is_linear(p->display_cfg->plane_descriptors[k].surface.tiling)) { in dcn5_calculate_swath_and_det_configuration()
810 if (dml2_core_utils_is_linear(p->display_cfg->plane_descriptors[k].surface.tiling)) { in dcn5_calculate_swath_and_det_configuration()
839 …gment_horizontal_contiguous(p->BytePerPixY[k], p->display_cfg->plane_descriptors[k].surface.tiling) in dcn5_calculate_swath_and_det_configuration()
849 …gment_horizontal_contiguous(p->BytePerPixC[k], p->display_cfg->plane_descriptors[k].surface.tiling) in dcn5_calculate_swath_and_det_configuration()
857 …gment_horizontal_contiguous(p->BytePerPixY[k], p->display_cfg->plane_descriptors[k].surface.tiling) in dcn5_calculate_swath_and_det_configuration()
859 …gment_horizontal_contiguous(p->BytePerPixC[k], p->display_cfg->plane_descriptors[k].surface.tiling) in dcn5_calculate_swath_and_det_configuration()
5393 enum dml2_swizzle_mode sw_mode = display_cfg->plane_descriptors[plane_idx].surface.tiling; in dcn5_rq_dlg_get_rq_reg()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| H A D | com.fuc | 518 // to correctly handle tiling.
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| /linux/Documentation/userspace-api/ |
| H A D | dma-buf-alloc-exchange.rst | 82 pixels at the start of vertically-consecutive tiling blocks. For linear
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 2901 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; in get_plane_info_update_type() local
2903 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { in get_plane_info_update_type()
2906 if (tiling->flags.avoid_full_update_on_tiling_change) { in get_plane_info_update_type()
|