| /linux/drivers/gpu/drm/tegra/ |
| H A D | fb.c | 38 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
44 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA; in tegra_fb_get_tiling()
46 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU; in tegra_fb_get_tiling()
53 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
54 tiling->value = 0; in tegra_fb_get_tiling()
58 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
59 tiling->value = 0; in tegra_fb_get_tiling()
63 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
64 tiling->value = 0; in tegra_fb_get_tiling()
68 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
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| H A D | plane.h | 49 struct tegra_bo_tiling tiling; member
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| H A D | plane.c | 63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
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| H A D | dc.c | 429 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
431 switch (window->tiling.mode) { in tegra_dc_setup_window()
448 switch (window->tiling.mode) { in tegra_dc_setup_window()
628 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
660 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
664 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
760 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
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| H A D | drm.h | 186 struct tegra_bo_tiling *tiling);
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| H A D | drm.c | 651 bo->tiling.mode = mode; in tegra_gem_set_tiling()
652 bo->tiling.value = value; in tegra_gem_set_tiling()
673 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
686 args->value = bo->tiling.value; in tegra_gem_get_tiling()
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| H A D | dc.h | 155 struct tegra_bo_tiling tiling; member
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| H A D | gem.c | 419 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_client_blt.c | 99 enum client_tiling tiling; member
137 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) in fast_blit_ok()
171 if (src->tiling == CLIENT_TILING_Y) { in prepare_blit()
175 } else if (src->tiling == CLIENT_TILING_X) { in prepare_blit()
182 if (dst->tiling == CLIENT_TILING_Y) { in prepare_blit()
186 } else if (dst->tiling == CLIENT_TILING_X) { in prepare_blit()
208 if (src->tiling == CLIENT_TILING_Y) in prepare_blit()
210 if (dst->tiling == CLIENT_TILING_Y) in prepare_blit()
228 if (src->tiling) { in prepare_blit()
234 if (dst->tiling) { in prepare_blit()
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| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_tiling.h | 16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
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| /linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_plane.c | 1221 u32 tiling, src_x, src_y; in vc4_plane_mode_set() local
1273 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
1331 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
1366 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
1372 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
1375 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
1378 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
1491 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
1529 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
1751 u32 tiling, src_x, src_y; in vc6_plane_mode_set() local
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.h | 40 u32 tiling; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/ |
| H A D | dml_top_display_cfg_types.h | 179 enum dml2_swizzle_mode tiling; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 389 surface->tiling = dml2_sw_64kb_2d; in populate_dml21_dummy_surface_cfg()
470 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
473 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
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| /linux/drivers/staging/media/ipu3/ |
| H A D | ipu3-abi.h | 919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-reserved.rst | 239 similitude with ``V4L2_PIX_FMT_MM21`` in term of alignment and tiling.
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| H A D | pixfmt-yuv-planar.rst | 383 Semi-planar YUV 4:2:0 formats, using macroblock tiling. The chroma plane is
458 ``V4L2_PIX_FMT_NV15_4L4`` Semi-planar 10-bit YUV 4:2:0 formats, using 4x4 tiling.
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| H A D | buffer.rst | 48 pixel format, the line stride, the tiling orientation or the rotation) is
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 167 - ``kms_plane_multiple@atomic-pipe-*-tiling-``
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| H A D | com.fuc | 518 // to correctly handle tiling.
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| /linux/Documentation/userspace-api/ |
| H A D | dma-buf-alloc-exchange.rst | 82 pixels at the start of vertically-consecutive tiling blocks. For linear
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 3781 || p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in CalculateSwathAndDETConfiguration()
3825 if (p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in CalculateSwathAndDETConfiguration()
7369 …t_setting_params->is_gfx11 = dml_get_gfx_version(display_cfg->plane_descriptors[k].surface.tiling); in dml_core_ms_prefetch_check()
8079 …if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear && dml_is_vertical_rotation… in dml_core_mode_support()
8087 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_support()
8206 if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) { in dml_core_mode_support()
8956 s->SurfParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_support()
9386 calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_support()
10577 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_programming()
10749 s->SurfaceParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 2835 const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; in get_plane_info_update_type() local
2837 if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { in get_plane_info_update_type()
2840 if (tiling->flags.avoid_full_update_on_tiling_change) { in get_plane_info_update_type()
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