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Searched refs:tile_width (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c856 unsigned int *tile_width, in intel_tile_dims() argument
862 *tile_width = tile_width_bytes / cpp; in intel_tile_dims()
872 unsigned int *tile_width, in intel_tile_block_dims() argument
875 intel_tile_dims(fb, color_plane, tile_width, tile_height); in intel_tile_block_dims()
883 unsigned int tile_width, tile_height; in intel_tile_row_size() local
885 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); in intel_tile_row_size()
971 unsigned int tile_width, in intel_adjust_tile_offset() argument
978 unsigned int pitch_pixels = pitch_tiles * tile_width; in intel_adjust_tile_offset()
988 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
1024 unsigned int tile_size, tile_width, tile_height; in intel_adjust_aligned_offset() local
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/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-mail.h258 s32 tile_width[4]; member
H A Dallegro-mail.c438 msg->tile_width[j] = src[i++]; in allegro_dec_encode_frame()
H A Dallegro-core.c1945 pps->column_width_minus1[i] = msg->tile_width[i] - 1; in allegro_hevc_write_pps()
/linux/drivers/gpu/drm/radeon/
H A Dr600_cs.c254 u32 tile_width = 8; in r600_get_array_mode_alignment() local
258 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; in r600_get_array_mode_alignment()
276 *pitch_align = max((u32)tile_width, in r600_get_array_mode_alignment()
284 *pitch_align = max((u32)macro_tile_width * tile_width, in r600_get_array_mode_alignment()
286 (values->blocksize * values->nsamples * tile_width))); in r600_get_array_mode_alignment()