Home
last modified time | relevance | path

Searched refs:tile_split (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Devergreen_cs.c1184 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1188 &tile_split); in evergreen_cs_handle_reg()
1190 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1448 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1452 &tile_split); in evergreen_cs_handle_reg()
1454 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1476 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1480 &tile_split); in evergreen_cs_handle_reg()
1482 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
2365 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_packet3_check() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c455 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
472 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c186 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local
191 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h392 enum tile_split_values tile_split; member
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c182 set_reg_field_value(value, info->gfx8.tile_split, in program_tiling()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1925 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v8_0_crtc_do_set_base()
H A Ddce_v6_0.c2003 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
2008 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
2013 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v6_0_crtc_do_set_base()
H A Ddce_v10_0.c1976 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1981 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1988 tile_split); in dce_v10_0_crtc_do_set_base()