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Searched refs:tile_split (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c1146 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1276 tile_split_bytes = 64 << tile_split; in dce4_crtc_do_set_base()
1286 tile_split); in dce4_crtc_do_set_base()
1331 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); in dce4_crtc_do_set_base()
H A Devergreen.c1113 unsigned *tile_split) in evergreen_tiling_fields() argument
1118 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c455 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
472 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c186 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local
191 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h392 enum tile_split_values tile_split; member
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c182 set_reg_field_value(value, info->gfx8.tile_split, in program_tiling()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1920 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1925 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1930 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v8_0_crtc_do_set_base()
H A Ddce_v10_0.c1981 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1986 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1993 tile_split); in dce_v10_0_crtc_do_set_base()
H A Ddce_v6_0.c2008 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
2013 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
2018 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v6_0_crtc_do_set_base()