Searched refs:tile_rows (Results 1 – 4 of 4) sorted by relevance
404 u8 tile_rows; member1297 tile->tile_rows = ctrl_tile->tile_rows; in vdec_av1_slice_setup_tile()1307 for (i = 0; i < tile->tile_rows + 1 && i < V4L2_AV1_MAX_TILE_ROWS + 1; i++) in vdec_av1_slice_setup_tile()1406 tile_group->num_tiles = tile->tile_cols * tile->tile_rows; in vdec_av1_slice_setup_tile_group()1420 vsi->frame.uh.tile.tile_rows); in vdec_av1_slice_setup_tile_group()
463 num_tiles = (u32)tile_info->tile_cols * tile_info->tile_rows; in rockchip_vpu981_av1_dec_prepare_run()621 context_update_x * tile_info->tile_rows + context_update_y; in rockchip_vpu981_av1_dec_set_tile_info()627 for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) { in rockchip_vpu981_av1_dec_set_tile_info()668 !!((tile_info->tile_cols > 1) || (tile_info->tile_rows > 1))); in rockchip_vpu981_av1_dec_set_tile_info()670 hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows); in rockchip_vpu981_av1_dec_set_tile_info()674 rockchip_vpu981_av1_tile_log2(tile_info->tile_rows)) in rockchip_vpu981_av1_dec_set_tile_info()
93 __entry->f.tile_info.tile_rows,
804 t->tile_rows > V4L2_AV1_MAX_TILE_ROWS) in validate_av1_tile_info()807 if ((u32)t->tile_cols * t->tile_rows > V4L2_AV1_MAX_TILE_COUNT) in validate_av1_tile_info()