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Searched refs:ti_clk_get_reg_addr (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/ti/
H A Ddpll.c252 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { in _register_dpll_x2()
316 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) in of_ti_dpll_setup()
325 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) in of_ti_dpll_setup()
332 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) in of_ti_dpll_setup()
335 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) in of_ti_dpll_setup()
340 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) in of_ti_dpll_setup()
350 if (ti_clk_get_reg_addr(node, ssc_clk_index++, in of_ti_dpll_setup()
354 if (ti_clk_get_reg_addr(node, ssc_clk_index++, in of_ti_dpll_setup()
H A Dapll.c212 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_dra7_apll_setup()
213 ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg); in of_dra7_apll_setup()
390 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_omap2_apll_setup()
391 ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg); in of_omap2_apll_setup()
392 ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg); in of_omap2_apll_setup()
H A Dgate.c139 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_gate_clk_setup()
176 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg)) in _of_ti_composite_gate_clk_setup()
H A Dinterface.c70 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_interface_clk_setup()
H A Dautoidle.c201 ret = ti_clk_get_reg_addr(node, 0, &clk->reg); in of_ti_clk_autoidle_setup()
H A Dclock.h217 int ti_clk_get_reg_addr(struct device_node *node, int index,
H A Dclk.c299 * ti_clk_get_reg_addr - get register address for a clock register
308 int ti_clk_get_reg_addr(struct device_node *node, int index, in ti_clk_get_reg_addr() function
H A Ddivider.c476 ret = ti_clk_get_reg_addr(node, 0, &div->reg); in ti_clk_divider_populate()