| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
189 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
190 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.c | 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
264 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
265 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
| H A D | dcn31_optc.c | 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
315 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
316 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 45 optc1->tg_shift->field_name, optc1->tg_mask->field_name
203 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) { in optc35_configure_crc()
448 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn35_timing_generator_init()
449 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn35_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
571 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
572 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/ |
| H A D | dcn401_optc.c | 22 optc1->tg_shift->field_name, optc1->tg_mask->field_name
536 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn401_timing_generator_init()
537 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn401_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.c | 40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
309 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { in optc1_program_timing()
320 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1622 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1623 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | optc.h | 50 const struct dcn_optc_mask *tg_mask; member
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| /linux/drivers/net/ethernet/mscc/ |
| H A D | ocelot_vcap.c | 46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
365 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
688 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
827 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 513 static const struct dcn_optc_mask tg_mask = { variable
772 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 271 uint32_t tg_mask = 0; in dcn32_update_clocks_update_dtb_dto() local
280 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
281 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 187 uint32_t tg_mask = 0; in dcn35_update_clocks_update_dtb_dto() local
196 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
197 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 272 static const struct dcn_optc_mask tg_mask = { variable
1055 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
|