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Searched refs:tg_inst (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
/linux/drivers/gpu/drm/amd/display/dc/virtual/
H A Dvirtual_stream_encoder.c93 int tg_inst) in virtual_dig_connect_to_otg() argument
98 int tg_inst, in virtual_setup_stereo_sync() argument
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c1488 int tg_inst, bool enable) in setup_stereo_sync() argument
1491 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1497 int tg_inst) in dig_connect_to_otg() argument
1501 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1507 uint32_t tg_inst = 0; in dig_source_otg() local
1510 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1512 return tg_inst; in dig_source_otg()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhw_shared.h92 int tg_inst; member
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c103 int dpp_inst, int opp_inst, int tg_inst, bool is_phantom_pipe) in capture_pipe_topology_data() argument
116 current_snapshot->pipe_log_lines[current_snapshot->line_count].tg_inst = tg_inst; in capture_pipe_topology_data()
3735 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
3750 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state()
3760 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
3763 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
3764 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
3766 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
3767 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
3774 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
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H A Ddc.c1462 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local
1469 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required()
1477 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required()
1790 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_boot_timing() local
1820 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_boot_timing()
1832 if (tg_inst >= dc->res_pool->timing_generator_count) { in dc_validate_boot_timing()
1837 if (tg_inst != link->link_enc->preferred_engine) { in dc_validate_boot_timing()
1842 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_boot_timing()
1927 tg_inst, &pix_clk_100hz); in dc_validate_boot_timing()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_stream_encoder.h687 int tg_inst, bool enable);
719 int tg_inst);
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h2417 uint8_t tg_inst; member
6063 uint32_t tg_inst; member