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Searched refs:tg_inst (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c177 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
205 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c1505 int tg_inst, bool enable) in setup_stereo_sync() argument
1508 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1514 int tg_inst) in dig_connect_to_otg() argument
1519 REG_UPDATE(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1521 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1527 uint32_t tg_inst = 0; in dig_source_otg() local
1531 REG_GET(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1533 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1535 return tg_inst; in dig_source_otg()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c108 int dpp_inst, int opp_inst, int tg_inst, bool is_phantom_pipe) in capture_pipe_topology_data() argument
121 current_snapshot->pipe_log_lines[current_snapshot->line_count].tg_inst = tg_inst; in capture_pipe_topology_data()
3995 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
4010 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state()
4020 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
4023 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
4024 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
4026 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
4027 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
4034 id_src[0] = tg_inst; in acquire_resource_from_hw_enabled_state()
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H A Ddc.c1532 unsigned int enc_inst, tg_inst = 0; in disable_vbios_mode_if_required() local
1539 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( in disable_vbios_mode_if_required()
1547 tg_inst, &pix_clk_100hz); in disable_vbios_mode_if_required()
1860 unsigned int tg_inst = 0; in dc_validate_boot_timing() local
1890 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_boot_timing()
1902 if (tg_inst >= dc->res_pool->timing_generator_count) { in dc_validate_boot_timing()
1907 if (tg_inst != link->link_enc->preferred_engine) { in dc_validate_boot_timing()
1912 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_boot_timing()
1996 if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) { in dc_validate_boot_timing()
1997 dsc = dc->res_pool->dscs[tg_inst]; in dc_validate_boot_timing()
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