/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
H A D | dcn10_dpp_cm.c | 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap() 120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap() 196 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap() 198 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap() 281 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix() 283 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix() 328 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field() 330 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field() 332 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field() [all …]
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H A D | dcn10_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 564 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument 574 dpp->tf_shift = tf_shift; in dpp1_construct()
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H A D | dcn10_dpp_dscl.c | 51 dpp->tf_shift->field_name, dpp->tf_mask->field_name 365 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
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H A D | dcn10_dpp.h | 1361 const struct dcn_dpp_shift *tf_shift; member 1523 const struct dcn_dpp_shift *tf_shift,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
H A D | dcn30_dpp_cm.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 173 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field() 175 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field() 178 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field() 180 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 182 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field() 184 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field() 187 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field() 189 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field() 191 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field() [all …]
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H A D | dcn30_dpp.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 134 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc() 136 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc() 673 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field() 675 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field() 677 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field() 679 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field() 682 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field() 684 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field() 686 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
H A D | dcn20_dpp_cm.c | 47 dpp->tf_shift->field_name, dpp->tf_mask->field_name 189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap() 191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap() 250 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap() 252 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap() 339 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc() 341 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc() 417 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 419 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 421 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() [all …]
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H A D | dcn20_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 411 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument 421 dpp->tf_shift = tf_shift; in dpp2_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
H A D | dcn35_dpp.c | 37 ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \ 131 const struct dcn35_dpp_shift *tf_shift, in dpp35_construct() argument 135 (const struct dcn3_dpp_shift *)(tf_shift), in dpp35_construct()
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H A D | dcn35_dpp.h | 59 const struct dcn35_dpp_shift *tf_shift,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
H A D | dcn201_dpp.h | 61 const struct dcn201_dpp_shift *tf_shift; member 80 const struct dcn201_dpp_shift *tf_shift,
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H A D | dcn201_dpp.c | 42 dpp->tf_shift->field_name, dpp->tf_mask->field_name 302 const struct dcn201_dpp_shift *tf_shift, in dpp201_construct() argument 312 dpp->tf_shift = tf_shift; in dpp201_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
H A D | dcn401_dpp_cm.c | 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 220 cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A; in dpp401_program_cursor_csc() 222 cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A; in dpp401_program_cursor_csc()
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H A D | dcn401_dpp.c | 43 dpp->tf_shift->field_name, dpp->tf_mask->field_name 266 const struct dcn401_dpp_shift *tf_shift, in dpp401_construct() argument 276 dpp->tf_shift = tf_shift; in dpp401_construct()
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H A D | dcn401_dpp.h | 658 const struct dcn401_dpp_shift *tf_shift; member 677 const struct dcn401_dpp_shift *tf_shift,
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H A D | dcn401_dpp_dscl.c | 51 dpp->tf_shift->field_name, dpp->tf_mask->field_name 379 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp401_dscl_set_scl_filter()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
H A D | dcn32_dpp.c | 151 const struct dcn3_dpp_shift *tf_shift, in dpp32_construct() argument 161 dpp->tf_shift = tf_shift; in dpp32_construct()
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H A D | dcn32_dpp.h | 36 const struct dcn3_dpp_shift *tf_shift,
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
H A D | dcn201_resource.c | 475 static const struct dcn201_dpp_shift tf_shift = { variable 638 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
H A D | dcn21_resource.c | 442 static const struct dcn2_dpp_shift tf_shift = { variable 510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
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