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Searched refs:tWHR_min (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/mtd/nand/raw/
H A Dnand_timings.c63 .tWHR_min = 120000,
108 .tWHR_min = 80000,
153 .tWHR_min = 80000,
198 .tWHR_min = 80000,
243 .tWHR_min = 80000,
288 .tWHR_min = 80000,
333 .tWHR_min = 80000,
375 .tWHR_min = 80000,
417 .tWHR_min = 80000,
459 .tWHR_min = 80000,
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H A Dnand_toshiba.c237 sdr->tWHR_min = 60000; in th58nvg2s3hbai4_choose_interface_config()
H A Dstm32_fmc2_nand.c1530 if (sdrt->tWHR_min > tset_mem && in stm32_fmc2_nfc_calc_timings()
1531 (thold_att < sdrt->tWHR_min - tset_mem)) in stm32_fmc2_nfc_calc_timings()
1532 thold_att = sdrt->tWHR_min - tset_mem; in stm32_fmc2_nfc_calc_timings()
H A Dtegra_nand.c806 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
H A Ddenali.c824 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_interface()
H A Dcadence-nand-controller.c2559 twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period); in cadence_nand_setup_sdr_interface()
2717 twhr_cnt = calc_cycl((nvddr->tWHR_min + if_skew), ddr_clk_ctrl_period); in cadence_nand_setup_nvddr_interface()
H A Dmtk_nand.c566 tw2r = timings->tWHR_min / 1000; in mtk_nfc_setup_interface()
/linux/include/linux/mtd/
H A Drawnand.h474 u32 tWHR_min; member
560 u32 tWHR_min; member