Home
last modified time | relevance | path

Searched refs:tWB_max (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/mtd/nand/raw/
H A Dnand_timings.c60 .tWB_max = 200000,
105 .tWB_max = 100000,
149 .tWB_max = 100000,
195 .tWB_max = 100000,
240 .tWB_max = 100000,
285 .tWB_max = 100000,
332 .tWB_max = 100000,
374 .tWB_max = 100000,
416 .tWB_max = 100000,
458 .tWB_max = 100000,
[all …]
H A Dstm32_fmc2_nand.c1305 ndelay(PSEC_TO_NSEC(timings->tWB_max)); in stm32_fmc2_nfc_waitrdy()
1521 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && in stm32_fmc2_nfc_calc_timings()
1522 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) in stm32_fmc2_nfc_calc_timings()
1523 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; in stm32_fmc2_nfc_calc_timings()
H A Dtegra_nand.c805 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
H A Dcadence-nand-controller.c2580 twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period); in cadence_nand_setup_sdr_interface()
2726 twb_cnt = calc_cycl((nvddr->tWB_max + board_delay), in cadence_nand_setup_nvddr_interface()
H A Dmeson_nand.c1266 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max), in meson_nfc_setup_interface()
/linux/include/linux/mtd/
H A Drawnand.h471 u32 tWB_max; member
559 u32 tWB_max; member