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Searched refs:tREH_min (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/mtd/nand/raw/
H A Dnand_timings.c52 .tREH_min = 30000,
97 .tREH_min = 15000,
142 .tREH_min = 15000,
187 .tREH_min = 10000,
232 .tREH_min = 10000,
277 .tREH_min = 7000,
586 spec_timings->tREH_min <= onfi_timings->tREH_min && in onfi_find_closest_sdr_mode()
H A Dintel-nand-controller.c214 trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min), in ebu_nand_set_timings()
221 trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min), in ebu_nand_set_timings()
H A Dstm32_fmc2_nand.c1468 if (sdrt->tREH_min > tset_mem && in stm32_fmc2_nfc_calc_timings()
1469 (thold_mem < sdrt->tREH_min - tset_mem)) in stm32_fmc2_nfc_calc_timings()
1470 thold_mem = sdrt->tREH_min - tset_mem; in stm32_fmc2_nfc_calc_timings()
H A Dcadence-nand-controller.c2443 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_sdr_interface()
2483 if (sdr->tREH_min >= trh) in cadence_nand_setup_sdr_interface()
2484 trh_cnt = calc_cycl(sdr->tREH_min, clk_period); in cadence_nand_setup_sdr_interface()
H A Dtegra_nand.c809 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); in tegra_nand_setup_timing()
H A Ddenali.c848 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), in denali_setup_interface()
H A Dmtk_nand.c571 twh = max(timings->tREH_min, timings->tWH_min) / 1000; in mtk_nfc_setup_interface()
/linux/include/linux/mtd/
H A Drawnand.h463 u32 tREH_min; member