Searched refs:sync_period (Results 1 – 9 of 9) sorted by relevance
213 u8 sync_period; /* for reg. */ member843 if (dcb->sync_period & WIDE_SYNC && in build_srb()954 dcb->sync_period = 0; in reset_dev_param()1179 DC395x_write8(acb, TRM_S1040_SCSI_SYNC, dcb->sync_period); in start_scsi()1650 if (dcb->sync_period & WIDE_SYNC) in data_out_phase0()1670 if (d_left_counter == 1 && dcb->sync_period & WIDE_SYNC in data_out_phase0()1695 (dcb->sync_period & WIDE_SYNC) ? 2 : 1; in data_out_phase0()1774 << ((srb->dcb->sync_period & WIDE_SYNC) ? 1 : in data_in_phase0()1784 if (srb->dcb->sync_period & WIDE_SYNC) in data_in_phase0()1822 if (fc == 0x40 && (srb->dcb->sync_period & WIDE_SYNC)) { in data_in_phase0()[all …]
55 #define sync_period seqstep macro
134 writeb(0, ®s->sync_period); in mac53c94_init()166 writeb(0, ®s->sync_period); in mac53c94_start()
1139 mb[3] |= nv->bus[bus].target[target].sync_period; in qla1280_set_target_parameters()1996 nv->bus[bus].target[target].sync_period = 9; in qla1280_set_target_defaults()2003 nv->bus[bus].target[target].sync_period = 10; in qla1280_set_target_defaults()2085 mb[3] |= nv->bus[bus].target[target].sync_period; in qla1280_config_target()
459 uint8_t sync_period; /* 42 */ member
95 u_short sync_period; /* 4*period factor */ member
94 tp->usr_period = (tn->sync_period + 3) / 4; in sym_Symbios_setup_target()167 tn->sync_period / 4, in sym_display_Symbios_nvram()
222 sync_threshold - vector of 2 INTEGERs: sync_threshold, sync_period229 modulus sync_period equals the threshold. The range of the230 threshold is from 0 to sync_period.232 When sync_period and sync_refresh_period are 0, send sync only
454 * - (2) if both sync_refresh_period and sync_period are 0 send sync only466 int sync_period; in ip_vs_sync_conn_needed() 520 sync_period = sysctl_sync_period(ipvs); in ip_vs_sync_conn_needed() 521 if (sync_period > 0) { in ip_vs_sync_conn_needed() 523 pkts % sync_period != sysctl_sync_threshold(ipvs)) in ip_vs_sync_conn_needed() 467 int sync_period; ip_vs_sync_conn_needed() local