| /linux/arch/arm/include/asm/mach/ |
| H A D | pci.h | 27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin); member
44 u8 (*swizzle)(struct pci_dev *, u8 *); member
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_client_blt.c | 37 int swizzle, subtile; in linear_x_y_to_ftiled_pos() local
73 swizzle = f_subtile_map[subtile]; in linear_x_y_to_ftiled_pos()
77 swizzle * F_SUBTILE_SIZE + in linear_x_y_to_ftiled_pos()
357 unsigned int swizzle; in tiled_offset() local
371 swizzle = gt->ggtt->bit_6_swizzle_x; in tiled_offset()
377 swizzle = I915_BIT_6_SWIZZLE_NONE; in tiled_offset()
387 swizzle = gt->ggtt->bit_6_swizzle_y; in tiled_offset()
390 switch (swizzle) { in tiled_offset()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1253 enum swizzle_mode_values swizzle = DC_SW_LINEAR; in dcn10_patch_unknown_plane_state() local
1256 swizzle = DC_SW_64KB_D; in dcn10_patch_unknown_plane_state()
1258 swizzle = DC_SW_64KB_S; in dcn10_patch_unknown_plane_state()
1260 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
1315 tiling_info->gfx9.swizzle = DC_SW_LINEAR; in dcn10_get_default_tiling_info()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_plane.c | 1330 unsigned int swizzle; in intel_ytile_get_offset() local
1340 swizzle = (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); in intel_ytile_get_offset()
1341 offset += swizzle * 4; in intel_ytile_get_offset()
1348 unsigned int swizzle; in intel_4tile_get_offset() local
1358 swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | in intel_4tile_get_offset()
1360 offset += swizzle * 4; in intel_4tile_get_offset()
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| /linux/drivers/gpu/drm/nouveau/dispnv50/ |
| H A D | wndw.c | 619 u32 blk_off, off, swizzle; in nv50_set_pixel_swizzle() local
628 swizzle = (x & 3) | (y & 3) << 2 | (x & 4) << 2 | (y & 4) << 3; in nv50_set_pixel_swizzle()
629 swizzle |= (x & 8) << 3 | (y >> 3) << 7; in nv50_set_pixel_swizzle()
630 off = blk_off + swizzle * 4; in nv50_set_pixel_swizzle()
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| H A D | dcn20_hubbub.c | 57 enum swizzle_mode_values swizzle, in hubbub2_dcc_support_swizzle() argument
66 switch (swizzle) { in hubbub2_dcc_support_swizzle()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| H A D | com.fuc | 416 // Calculates the hw swizzle mask and adjusts the surface's xcnt to match
419 // zero out a chunk of the stack to store the swizzle into
435 // convert FORMAT swizzle mask to hw swizzle mask
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| H A D | dcn401_hubbub.h | 163 enum swizzle_mode_addr3_values swizzle,
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 291 input.swizzle_mode = tiling_info->gfx9.swizzle; in amdgpu_dm_plane_validate_dcc()
324 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
377 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
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| H A D | amdgpu_dm.c | 8125 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 470 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
473 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1253 enum swizzle_mode_values swizzle, in swizzle_to_dml_params() argument
1256 switch (swizzle) { in swizzle_to_dml_params()
1687 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
1688 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 936 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()
940 switch (in->tiling_info.gfx_addr3.swizzle) { in populate_dml_surface_cfg_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 2255 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S; in dcn20_patch_unknown_plane_state()
2257 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D; in dcn20_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 1421 enum dc_cm_lut_swizzle swizzle; member
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 4450 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| H A D | dc_hw_sequencer.c | 2091 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
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