Searched refs:swizzle (Results 1 – 12 of 12) sorted by relevance
78 vs_format->swizzle = VSDC_SWIZZLE_RGBA; in drm_format_to_vs_format()88 vs_format->swizzle = VSDC_SWIZZLE_ABGR; in drm_format_to_vs_format()97 vs_format->swizzle = VSDC_SWIZZLE_BGRA; in drm_format_to_vs_format()101 vs_format->swizzle = VSDC_SWIZZLE_ARGB; in drm_format_to_vs_format()
124 VSDC_FB_CONFIG_SWIZZLE(vs_state->format.swizzle)); in vs_primary_plane_atomic_update()
27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin); member44 u8 (*swizzle)(struct pci_dev *, u8 *); member
37 int swizzle, subtile; in linear_x_y_to_ftiled_pos() local73 swizzle = f_subtile_map[subtile]; in linear_x_y_to_ftiled_pos()77 swizzle * F_SUBTILE_SIZE + in linear_x_y_to_ftiled_pos()357 unsigned int swizzle; in tiled_offset() local371 swizzle = gt->ggtt->bit_6_swizzle_x; in tiled_offset()377 swizzle = I915_BIT_6_SWIZZLE_NONE; in tiled_offset()387 swizzle = gt->ggtt->bit_6_swizzle_y; in tiled_offset()390 switch (swizzle) { in tiled_offset()
416 // Calculates the hw swizzle mask and adjusts the surface's xcnt to match419 // zero out a chunk of the stack to store the swizzle into435 // convert FORMAT swizzle mask to hw swizzle mask
312 input.swizzle_mode = tiling_info->gfx9.swizzle; in amdgpu_dm_plane_validate_dcc() 346 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_validate_dcc() 400 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers() 924 /* R_X swizzle modes are the best for rendering and DCC requires them. */ in amdgpu_dm_plane_add_gfx11_modifiers() 1876 * For D swizzle the canonical modifier depends on the bpp, so check in amdgpu_dm_plane_format_mod_supported()
2205 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
941 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()945 switch (in->tiling_info.gfx_addr3.swizzle) { in populate_dml_surface_cfg_from_plane_state()
1808 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D; in dcn401_patch_unknown_plane_state()1998 tiling_info->gfx_addr3.swizzle = DC_ADDR3_SW_LINEAR; in dcn401_get_default_tiling_info()
93 tiling_info->gfx9.swizzle = 9; in dm_test_init_validate_dcc_inputs()605 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.swizzle, 0U); in dm_test_fill_gfx9_plane_attributes_from_modifiers()
4811 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
7649 state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle; in dc_capture_register_software_state()