| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 642 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
652 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
654 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
656 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame()
657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame()
658 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
659 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
661 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
662 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 96 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
562 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_set_output_transfer_func()
631 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in enable_stream_timing_calc()
679 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
688 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
689 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
697 …dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg-… in dcn401_enable_stream_timing()
704 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
708 &pipe_ctx->stream_res.pix_clk_params, in dcn401_enable_stream_timing()
725 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn401_enable_stream_timing()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 543 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
546 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; in update_psp_stream_config()
549 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; in update_psp_stream_config()
552 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; in update_psp_stream_config()
671 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream()
713 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
715 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
720 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in link_set_dsc_on_stream()
730 …DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_en… in link_set_dsc_on_stream()
732 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) in link_set_dsc_on_stream()
[all …]
|
| H A D | link_hwss_hpo_frl.c | 31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 313 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
322 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
327 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
348 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
388 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
434 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc()
524 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
545 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
547 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
550 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1482 params = &opp_heads[i]->stream_res.test_pattern_params; in resource_build_test_pattern_params()
2206 if (otg_master->stream_res.tg) in resource_get_odm_slice_dst_width()
2208 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) || in resource_get_odm_slice_dst_width()
2248 struct output_pixel_processor *opp = opp_head->stream_res.opp; in resource_get_odm_slice_src_rect()
2325 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp) in resource_is_odm_topology_changed()
2369 pipe->stream_res.opp->inst, in resource_log_pipe()
2370 pipe->stream_res.tg->inst); in resource_log_pipe()
2373 pipe->stream_res.opp->inst, in resource_log_pipe()
2374 pipe->stream_res.tg->inst, is_phantom_pipe); in resource_log_pipe()
2380 pipe->stream_res.opp->inst, in resource_log_pipe()
[all …]
|
| H A D | dc_stream.c | 537 pipe_ctx->stream_res.tg->funcs->program_manual_trigger) { in dc_stream_program_cursor_position()
538 pipe_ctx->stream_res.tg->funcs->program_manual_trigger( in dc_stream_program_cursor_position()
539 pipe_ctx->stream_res.tg); in dc_stream_program_cursor_position()
728 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
796 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_scanoutpos()
|
| H A D | dc_hw_sequencer.c | 701 if (pipe_ctx && pipe_ctx->stream_res.tg && in set_drr_and_clear_adjust_pending()
702 pipe_ctx->stream_res.tg->funcs->set_drr) in set_drr_and_clear_adjust_pending()
703 pipe_ctx->stream_res.tg->funcs->set_drr( in set_drr_and_clear_adjust_pending()
704 pipe_ctx->stream_res.tg, params); in set_drr_and_clear_adjust_pending()
884 …block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp-… in hwss_build_fast_sequence()
891 …equence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
1954 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) in hwss_program_manual_trigger()
1955 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); in hwss_program_manual_trigger()
2125 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); in hwss_wait_for_all_blank_complete()
2140 tg = otg_master->stream_res.tg; in hwss_wait_for_odm_update_pending_complete()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 180 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
213 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
214 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe()
247 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
248 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1274 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1290 …else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt =… in get_pixel_clock_parameters()
1300 if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container && in get_pixel_clock_parameters()
1301 pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) || in get_pixel_clock_parameters()
1320 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dcn20_build_pipe_pix_clk_params()
1323 &pipe_ctx->stream_res.pix_clk_params, in dcn20_build_pipe_pix_clk_params()
1369 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1430 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1433 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
1436 if (!pipe_ctx->stream_res.dsc) { in dcn20_add_dsc_to_stream_resource()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 902 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
926 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
929 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1148 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1152 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1163 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1171 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1181 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1182 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1194 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.c | 347 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings()
348 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
351 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings()
352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1037 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1071 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1135 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn10_acquire_free_pipe_for_layer()
1136 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; in dcn10_acquire_free_pipe_for_layer()
1137 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn10_acquire_free_pipe_for_layer()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
174 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
186 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
202 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1573 sec_pipe->stream_res.dsc = NULL; in dcn30_split_stream_for_mpc_or_odm()
1592 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1594 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; in dcn30_split_stream_for_mpc_or_odm()
1596 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn30_split_stream_for_mpc_or_odm()
1597 ASSERT(sec_pipe->stream_res.dsc); in dcn30_split_stream_for_mpc_or_odm()
1598 if (sec_pipe->stream_res.dsc == NULL) in dcn30_split_stream_for_mpc_or_odm()
1777 if (pipe->stream_res.dsc) in dcn30_internal_validate_bw()
1778 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn30_internal_validate_bw()
1780 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn30_internal_validate_bw()
1795 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn30_internal_validate_bw()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 2805 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2806 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2864 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2865 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2895 free_pipe->stream_res.tg = otg_master->stream_res.tg; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2896 free_pipe->stream_res.dsc = NULL; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2897 free_pipe->stream_res.opp = pool->opps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2908 &free_pipe->stream_res.dsc, in dcn32_acquire_free_pipe_as_secondary_opp_head()
2910 ASSERT(free_pipe->stream_res.dsc); in dcn32_acquire_free_pipe_as_secondary_opp_head()
2911 if (free_pipe->stream_res.dsc == NULL) { in dcn32_acquire_free_pipe_as_secondary_opp_head()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 162 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in is_dp2p0_output_encoder()
164 return (pipe_ctx->stream_res.hpo_dp_stream_enc && in is_dp2p0_output_encoder()
258 ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF); in populate_pipe_ctx_dlg_params_from_dml()
259 pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst; in populate_pipe_ctx_dlg_params_from_dml()
|
| H A D | dml2_translation_helper.c | 1000 temp_pipe->stream_res = pipe->stream_res; in get_scaler_data_for_plane()
1290 current_pipe_context->stream_res.hpo_dp_stream_enc && in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
1293 …dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_strea… in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
|
| H A D | dml2_dc_resource_mgmt.c | 323 existing_state->res_ctx.pipe_ctx[i].stream_res.tg) in find_last_resort_pipe_candidates()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 1052 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn201_acquire_free_pipe_for_layer()
1053 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn201_acquire_free_pipe_for_layer()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 1856 sec_pipe->stream_res.dsc = NULL; in dcn32_split_stream_for_mpc_or_odm()
1876 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1878 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; in dcn32_split_stream_for_mpc_or_odm()
1880 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn32_split_stream_for_mpc_or_odm()
1881 ASSERT(sec_pipe->stream_res.dsc); in dcn32_split_stream_for_mpc_or_odm()
1882 if (sec_pipe->stream_res.dsc == NULL) in dcn32_split_stream_for_mpc_or_odm()
1954 …memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct str… in dcn32_apply_merge_split_flags_helper()
1968 if (pipe->stream_res.dsc) in dcn32_apply_merge_split_flags_helper()
1969 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_apply_merge_split_flags_helper()
1971 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_apply_merge_split_flags_helper()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 190 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in check_dp2p0_output_encoder()
191 return (pipe_ctx->stream_res.hpo_dp_stream_enc && in check_dp2p0_output_encoder()
|
| H A D | dml21_translation_helper.c | 495 temp_pipe->stream_res = pipe->stream_res; in get_scaler_data_for_plane()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_capability.c | 381 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in dp_is_128b_132b_signal()
382 return (pipe_ctx->stream_res.hpo_dp_stream_enc && in dp_is_128b_132b_signal()
|