| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 638 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
649 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
650 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
652 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame()
654 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
655 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
658 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 96 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
619 struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; in dcn401_set_mcm_luts()
672 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_set_output_transfer_func()
740 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in enable_stream_timing_calc()
788 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
797 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
798 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
806 …dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg-… in dcn401_enable_stream_timing()
813 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
817 &pipe_ctx->stream_res.pix_clk_params, in dcn401_enable_stream_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 232 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
237 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
259 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
263 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
287 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
289 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
291 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
293 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 383 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
393 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
394 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
395 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
397 if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame()
398 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dcn31_update_info_frame()
399 pipe_ctx->stream_res.hpo_dp_stream_enc, in dcn31_update_info_frame()
400 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
402 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame()
403 pipe_ctx->stream_res.hpo_dp_stream_enc, in dcn31_update_info_frame()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
370 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
372 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
376 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream()
384 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
385 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
391 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
392 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder()
92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_attribute()
181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output()
182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output()
189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet()
190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet()
195 if (pipe_ctx->stream_res.audio) in disable_hpo_dp_audio_packet()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 112 !pipe_ctx->stream_res.tg || in dcn10_wait_for_pipe_update_if_needed()
113 !pipe_ctx->stream_res.stream_enc) in dcn10_wait_for_pipe_update_if_needed()
123 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_wait_for_pipe_update_if_needed()
185 !pipe_ctx->stream_res.tg || in dcn10_set_wait_for_update_needed_for_pipe()
186 !pipe_ctx->stream_res.stream_enc) in dcn10_set_wait_for_update_needed_for_pipe()
195 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_set_wait_for_update_needed_for_pipe()
232 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
817 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
1200 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
1204 &pipe_ctx->stream_res.pix_clk_params, in dcn10_enable_stream_timing()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 416 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
452 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
488 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
561 if (pipe_ctx->stream_res.opp && in dcn32_set_input_transfer_func()
562 pipe_ctx->stream_res.opp->ctx && in dcn32_set_input_transfer_func()
574 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
1022 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream()
1051 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
1058 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
1078 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in dcn32_update_dsc_on_stream()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 680 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
683 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; in update_psp_stream_config()
686 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; in update_psp_stream_config()
689 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; in update_psp_stream_config()
808 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream()
850 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
852 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
857 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in link_set_dsc_on_stream()
867 …DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_en… in link_set_dsc_on_stream()
869 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) in link_set_dsc_on_stream()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 262 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
346 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
363 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_program_gamut_remap()
399 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
838 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) { in dcn30_set_avmute()
839 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( in dcn30_set_avmute()
840 pipe_ctx->stream_res.stream_enc, in dcn30_set_avmute()
844 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { in dcn30_set_avmute()
845 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
846 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 313 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
322 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
327 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
348 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
388 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
434 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc()
524 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
545 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
547 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
550 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1475 params = &opp_heads[i]->stream_res.test_pattern_params; in resource_build_test_pattern_params()
2196 if (otg_master->stream_res.tg) in resource_get_odm_slice_dst_width()
2198 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) || in resource_get_odm_slice_dst_width()
2238 struct output_pixel_processor *opp = opp_head->stream_res.opp; in resource_get_odm_slice_src_rect()
2315 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp) in resource_is_odm_topology_changed()
2359 pipe->stream_res.opp->inst, in resource_log_pipe()
2360 pipe->stream_res.tg->inst); in resource_log_pipe()
2363 pipe->stream_res.opp->inst, in resource_log_pipe()
2364 pipe->stream_res.tg->inst, is_phantom_pipe); in resource_log_pipe()
2370 pipe->stream_res.opp->inst, in resource_log_pipe()
[all …]
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| H A D | dc.c | 434 if (pipe->stream == stream && pipe->stream_res.tg) { in set_long_vtotal()
498 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
540 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_get_last_used_drr_vtotal()
544 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { in dc_stream_get_last_used_drr_vtotal()
545 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); in dc_stream_get_last_used_drr_vtotal()
614 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_crc_window()
680 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_multiple_crc_window()
761 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
803 tg = pipe->stream_res.tg; in dc_stream_get_crc()
824 pipe_ctx->stream_res.opp->dyn_expansion = option; in dc_stream_set_dyn_expansion()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 180 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
213 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
214 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe()
247 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
248 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1239 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1255 …else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt =… in get_pixel_clock_parameters()
1265 if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container && in get_pixel_clock_parameters()
1266 pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) || in get_pixel_clock_parameters()
1285 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dcn20_build_pipe_pix_clk_params()
1288 &pipe_ctx->stream_res.pix_clk_params, in dcn20_build_pipe_pix_clk_params()
1333 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1394 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1397 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
1400 if (!pipe_ctx->stream_res.dsc) { in dcn20_add_dsc_to_stream_resource()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 223 old_pipe->stream_res.tg == new_pipe->stream_res.tg && in dcn35_disable_otg_wa()
228 new_pipe->stream_res.stream_enc && in dcn35_disable_otg_wa()
229 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && in dcn35_disable_otg_wa()
230 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); in dcn35_disable_otg_wa()
243 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn35_disable_otg_wa()
244 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa()
248 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa()
267 if (pipe_ctx->stream_res.tg && in dcn35_update_clocks_update_dtb_dto()
268 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
269 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_panel_replay.c | 134 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; in dp_setup_panel_replay()
222 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg) in dp_pr_get_panel_inst()
223 *inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst; in dp_pr_get_panel_inst()
312 if (pipe_ctx->stream_res.tg) in dp_pr_copy_settings()
313 cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; in dp_pr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 900 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
924 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
927 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1142 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1146 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1157 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1165 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1175 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1176 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1188 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 131 if (pipe->stream_res.dsc) in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
134 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
148 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
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| H A D | dcn32_resource.c | 2761 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2762 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2820 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2821 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2851 free_pipe->stream_res.tg = otg_master->stream_res.tg; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2852 free_pipe->stream_res.dsc = NULL; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2853 free_pipe->stream_res.opp = pool->opps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2864 &free_pipe->stream_res.dsc, in dcn32_acquire_free_pipe_as_secondary_opp_head()
2866 ASSERT(free_pipe->stream_res.dsc); in dcn32_acquire_free_pipe_as_secondary_opp_head()
2867 if (free_pipe->stream_res.dsc == NULL) { in dcn32_acquire_free_pipe_as_secondary_opp_head()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.c | 347 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings()
348 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
351 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings()
352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1003 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1033 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1037 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1099 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn10_acquire_free_pipe_for_layer()
1100 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; in dcn10_acquire_free_pipe_for_layer()
1101 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn10_acquire_free_pipe_for_layer()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 279 if (pipe_ctx->stream_res.tg && in dcn32_update_clocks_update_dtb_dto()
280 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
281 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
283 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; in dcn32_update_clocks_update_dtb_dto()
375 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist()
393 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist()
428 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist()
444 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
174 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
186 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
202 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
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