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Searched refs:stream_res (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c99 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
109 &pipes[i]->stream_res.pix_clk_params, in dp_retrain_link_dp_test()
113 if (pipes[i]->stream_res.audio != NULL) { in dp_retrain_link_dp_test()
118 pipes[i]->stream_res.audio->inst); in dp_retrain_link_dp_test()
120 pipes[i]->stream_res.audio->funcs->az_configure( in dp_retrain_link_dp_test()
121 pipes[i]->stream_res.audio, in dp_retrain_link_dp_test()
128 pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio && in dp_retrain_link_dp_test()
130 pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio(pipes[i]->stream_res.audio); in dp_retrain_link_dp_test()
141 pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
489 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in set_crtc_test_pattern()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c637 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
647 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
649 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
651 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame()
652 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
654 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
656 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
657 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c91 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
613 struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; in dcn401_set_mcm_luts()
664 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_set_output_transfer_func()
732 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in enable_stream_timing_calc()
780 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
789 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
790 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
798 …dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg-… in dcn401_enable_stream_timing()
805 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
809 &pipe_ctx->stream_res.pix_clk_params, in dcn401_enable_stream_timing()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c231 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
236 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
258 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
262 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
286 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
287 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
290 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
291 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
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/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_dp.c37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder()
92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_attribute()
181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output()
182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output()
189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet()
190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet()
195 if (pipe_ctx->stream_res.audio) in disable_hpo_dp_audio_packet()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; in update_psp_stream_config()
685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; in update_psp_stream_config()
688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; in update_psp_stream_config()
807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream()
849 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
851 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
856 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in link_set_dsc_on_stream()
865 …DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_en… in link_set_dsc_on_stream()
867 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) in link_set_dsc_on_stream()
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H A Dlink_hwss_hpo_frl.c31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c310 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
319 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
324 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
345 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
385 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
431 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc()
521 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
542 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
544 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
547 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1475 params = &opp_heads[i]->stream_res.test_pattern_params; in resource_build_test_pattern_params()
2196 if (otg_master->stream_res.tg) in resource_get_odm_slice_dst_width()
2198 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) || in resource_get_odm_slice_dst_width()
2238 struct output_pixel_processor *opp = opp_head->stream_res.opp; in resource_get_odm_slice_src_rect()
2315 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp) in resource_is_odm_topology_changed()
2359 pipe->stream_res.opp->inst, in resource_log_pipe()
2360 pipe->stream_res.tg->inst); in resource_log_pipe()
2363 pipe->stream_res.opp->inst, in resource_log_pipe()
2364 pipe->stream_res.tg->inst, is_phantom_pipe); in resource_log_pipe()
2370 pipe->stream_res.opp->inst, in resource_log_pipe()
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H A Ddc.c434 if (pipe->stream == stream && pipe->stream_res.tg) { in set_long_vtotal()
498 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
540 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_get_last_used_drr_vtotal()
544 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { in dc_stream_get_last_used_drr_vtotal()
545 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); in dc_stream_get_last_used_drr_vtotal()
614 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_crc_window()
680 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_multiple_crc_window()
759 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
801 tg = pipe->stream_res.tg; in dc_stream_get_crc()
822 pipe_ctx->stream_res.opp->dyn_expansion = option; in dc_stream_set_dyn_expansion()
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H A Ddc_hw_sequencer.c701 if (pipe_ctx && pipe_ctx->stream_res.tg && in set_drr_and_clear_adjust_pending()
702 pipe_ctx->stream_res.tg->funcs->set_drr) in set_drr_and_clear_adjust_pending()
703 pipe_ctx->stream_res.tg->funcs->set_drr( in set_drr_and_clear_adjust_pending()
704 pipe_ctx->stream_res.tg, params); in set_drr_and_clear_adjust_pending()
872 …block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp-… in hwss_build_fast_sequence()
879 …equence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
1939 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) in hwss_program_manual_trigger()
1940 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); in hwss_program_manual_trigger()
2100 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); in hwss_wait_for_all_blank_complete()
2115 tg = otg_master->stream_res.tg; in hwss_wait_for_odm_update_pending_complete()
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H A Ddc_stream.c684 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
752 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_scanoutpos()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c131 if (pipe->stream_res.dsc) in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
134 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
148 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
174 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
186 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist()
202 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c199 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in get_max_pixel_clock_for_all_paths()
200 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths()
206 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths()
207 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths()
524 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
H A Ddmub_replay.c157 if (pipe_ctx->stream_res.tg) in dmub_replay_copy_settings()
158 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_replay_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c807 pipe_ctx[i].stream_res.tg->inst + 1; in edp_setup_psr()
1041 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; in edp_setup_panel_replay()
1147 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; in edp_setup_freesync_replay()
1319 abm = pipe_ctx->stream_res.abm; in get_abm_from_stream_res()
H A Dlink_dp_capability.c381 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in dp_is_128b_132b_signal()
382 return (pipe_ctx->stream_res.hpo_dp_stream_enc && in dp_is_128b_132b_signal()
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c219 tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()