/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
H A D | dcn314_hwseq.c | 74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() 99 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream() 101 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream() 105 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream() 113 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream() 114 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream() 120 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream() 121 pipe_ctx->stream_res.tg, in update_dsc_on_stream() 125 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream() 127 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
H A D | link_hwss_dio.c | 42 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size() 52 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder() 55 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder() 67 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle); in setup_dio_stream_encoder() 75 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in reset_dio_stream_encoder() 89 pipe_ctx->stream_res.stream_enc->id, in reset_dio_stream_encoder() 100 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_attribute() 107 pipe_ctx->stream_res.tg->inst, in setup_dio_stream_attribute() 122 pipe_ctx->stream_res.audio != NULL); in setup_dio_stream_attribute() 206 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( in setup_dio_audio_output() [all …]
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H A D | link_hwss_hpo_dp.c | 37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size() 51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width() 76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder() 85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder() 92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_attribute() 181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output() 182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output() 189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet() 190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet() 195 if (pipe_ctx->stream_res.audio) in disable_hpo_dp_audio_packet() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
H A D | dce110_hwseq.c | 636 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame() 646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame() 647 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame() 648 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame() 650 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame() 651 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame() 652 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame() 653 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame() 655 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame() 656 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
H A D | dcn35_hwseq.c | 323 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() 341 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream() 348 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream() 363 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream() 365 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream() 369 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream() 377 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream() 378 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream() 384 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream() 385 pipe_ctx->stream_res.tg, in update_dsc_on_stream() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
H A D | dcn31_hwseq.c | 385 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame() 395 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame() 396 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame() 397 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame() 399 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame() 400 pipe_ctx->stream_res.hpo_dp_stream_enc, in dcn31_update_info_frame() 401 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame() 404 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame() 405 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dcn31_update_info_frame() 406 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
H A D | link_dp_cts.c | 428 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in set_crtc_test_pattern() 436 controller_test_pattern = pipe_ctx->stream_res.test_pattern_params.test_pattern; in set_crtc_test_pattern() 447 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern() 449 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern() 455 controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space; in set_crtc_test_pattern() 464 tp_params = &odm_pipe->stream_res.test_pattern_params; in set_crtc_test_pattern() 465 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern() 486 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern() 488 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern() 496 tp_params = &odm_pipe->stream_res.test_pattern_params; in set_crtc_test_pattern() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
H A D | dcn10_hwseq.c | 109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes() 599 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur() 982 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing() 986 &pipe_ctx->stream_res.pix_clk_params, in dcn10_enable_stream_timing() 1001 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn10_enable_stream_timing() 1002 pipe_ctx->stream_res.tg, in dcn10_enable_stream_timing() 1016 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing() 1018 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( in dcn10_enable_stream_timing() 1019 pipe_ctx->stream_res.opp, in dcn10_enable_stream_timing() 1035 if (pipe_ctx->stream_res.tg->funcs->set_blank_color) in dcn10_enable_stream_timing() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
H A D | dce_hwseq.c | 56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock() 57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock() 60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock() 71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock() 76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock() 82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock() 83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.c | 249 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut() 332 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func() 349 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_program_gamut_remap() 385 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func() 824 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) { in dcn30_set_avmute() 825 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( in dcn30_set_avmute() 826 pipe_ctx->stream_res.stream_enc, in dcn30_set_avmute() 830 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { in dcn30_set_avmute() 831 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute() 832 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
H A D | dcn201_hwseq.c | 310 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw() 319 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw() 324 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw() 345 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw() 385 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect() 431 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc() 521 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc() 542 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock() 544 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock() 547 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_hw_sequencer.c | 128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc() 192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility() 200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color() 251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler() 260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler() 261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
H A D | dcn35_clk_mgr.c | 146 old_pipe->stream_res.tg == new_pipe->stream_res.tg && in dcn35_disable_otg_wa() 151 new_pipe->stream_res.stream_enc && in dcn35_disable_otg_wa() 152 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && in dcn35_disable_otg_wa() 153 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); in dcn35_disable_otg_wa() 171 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn35_disable_otg_wa() 172 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa() 176 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn35_disable_otg_wa() 195 if (pipe_ctx->stream_res.tg && in dcn35_update_clocks_update_dtb_dto() 196 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto() 197 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
H A D | dce_clk_mgr.c | 180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths() 181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths() 187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths() 188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
H A D | dce110_resource.c | 895 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters() 919 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param() 922 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param() 1137 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay() 1141 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay() 1152 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay() 1160 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay() 1170 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay() 1171 pipe_ctx->stream_res.tg, in dce110_acquire_underlay() 1183 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 118 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn316_disable_otg_wa() 119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa() 123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
H A D | dcn32_resource_helpers.c | 131 if (pipe->stream_res.dsc) in dcn32_merge_pipes_for_subvp() 132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp() 134 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp() 148 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dmub_psr.c | 347 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings() 348 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings() 351 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings() 352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
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H A D | dce_clk_mgr.c | 199 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in get_max_pixel_clock_for_all_paths() 200 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths() 206 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths() 207 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths() 524 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 279 if (pipe_ctx->stream_res.tg && in dcn32_update_clocks_update_dtb_dto() 280 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto() 281 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto() 283 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; in dcn32_update_clocks_update_dtb_dto() 375 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist() 393 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist() 428 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist() 444 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist()
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/linux/drivers/gpu/drm/amd/display/dc/link/ |
H A D | link_hwss_hpo_frl.c | 31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_mall_phantom.c | 124 if (pipe->stream_res.dsc) in merge_pipes_for_subvp() 125 …lease_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc); in merge_pipes_for_subvp() 127 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in merge_pipes_for_subvp() 141 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in merge_pipes_for_subvp()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
H A D | dcn20_clk_mgr.c | 156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist() 174 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist() 186 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn20_update_clocks_update_dentist() 202 pipe_ctx->stream_res.tg->inst); in dcn20_update_clocks_update_dentist()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 116 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn315_disable_otg_wa() 119 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn315_disable_otg_wa()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_debugfs.c | 1280 if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) in odm_combine_segments_show() 1281 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); in odm_combine_segments_show() 1554 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read() 1740 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read() 1924 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read() 2104 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_bits_per_pixel_read() 2279 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_width_read() 2333 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_height_read() 2402 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_chunk_size_read() 2471 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_bpg_offset_read()
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