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Searched refs:stream_descriptors (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c161 double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc; in get_stream_output_bpp()
162 if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) { in get_stream_output_bpp()
163 switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) { in get_stream_output_bpp()
178 } else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) { in get_stream_output_bpp()
179 out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16; in get_stream_output_bpp()
184 DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable); in get_stream_output_bpp()
436 PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000); in PixelClockAdjustmentForProgressiveToInterlaceUnit()
437 if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) { in PixelClockAdjustmentForProgressiveToInterlaceUnit()
439 //display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz = 2 * display_cfg->stream_descriptors[display_cf in PixelClockAdjustmentForProgressiveToInterlaceUnit()
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H A Ddml2_core_utils.c340 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
342 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
364 …DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[disp… in dml2_core_utils_get_stream_output_bpp()
633 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in dml2_core_utils_expand_implict_subvp()
639 …create_phantom_stream_from_main_stream(&svp_expanded_display_cfg->stream_descriptors[svp_expanded_… in dml2_core_utils_expand_implict_subvp()
656 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in dml2_core_utils_expand_implict_subvp()
657 …phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main… in dml2_core_utils_expand_implict_subvp()
H A Ddml2_core_dcn4.c327 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
333 create_phantom_stream_from_main_stream(&svp_expanded_display_cfg->stream_descriptors[svp_expanded_display_cfg->num_streams], in expand_implict_subvp()
350 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in expand_implict_subvp()
351 phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]]; in expand_implict_subvp()
398 main_stream = &svp_expanded_display_cfg->stream_descriptors[stream_index]; in pack_mode_programming_params_with_implicit_subvp()
399 phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[stream_index]]; in pack_mode_programming_params_with_implicit_subvp()
402 programming->stream_programming[stream_index].stream_descriptor = &programming->display_config.stream_descriptors[stream_index]; in pack_mode_programming_params_with_implicit_subvp()
732 in_out->programming->stream_programming[main_stream_index].stream_descriptor = &in_out->programming->display_config.stream_descriptors[main_stream_index]; in core_dcn4_mode_programming()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c338 if (!increase_odm_combine_factor(&in_out->optimized_display_cfg->stream_descriptors[i].overrides.odm_mode, in pmo_dcn4_fams2_optimize_dcc_mcache()
802 if (display_config->stream_descriptors[i].overrides.disable_dynamic_odm) in pmo_dcn4_fams2_init_for_vmin()
811 else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2)) in pmo_dcn4_fams2_init_for_vmin()
817 else if (!is_dp_encoder(display_config->stream_descriptors[i].output.output_encoder)) in pmo_dcn4_fams2_init_for_vmin()
846 odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz in find_highest_odm_load_stream_index()
890 stream_descriptor = &in_out->optimized_display_config->display_config.stream_descriptors[stream_index]; in pmo_dcn4_fams2_optimize_for_vmin()
904 if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) { in pmo_dcn4_fams2_optimize_for_vmin()
923 if (is_h_timing_divisible_by(&display_config->stream_descriptors[stream_index].timing, 4)) { in pmo_dcn4_fams2_optimize_for_vmin()
982 master_timing = &display_config->display_config.stream_descriptors[i].timing; in build_synchronized_timing_groups()
1007 &display_config->display_config.stream_descriptors[ in build_synchronized_timing_groups()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c823 populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx); in dml21_map_dc_state_into_dml_display_cfg()
824 populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]); in dml21_map_dc_state_into_dml_display_cfg()
825 populate_dml21_stream_overrides_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]); in dml21_map_dc_state_into_dml_display_cfg()
827 dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.fclk_pstate = dml2_twait_budgeting_setting_if_needed; in dml21_map_dc_state_into_dml_display_cfg()
828 dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.uclk_pstate = dml2_twait_budgeting_setting_if_needed; in dml21_map_dc_state_into_dml_display_cfg()
829 dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.stutter_enter_exit = dml2_twait_budgeting_setting_if_needed; in dml21_map_dc_state_into_dml_display_cfg()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_display_cfg_types.h458 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES]; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c475 …if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream… in are_timings_trivially_synchronizable()
483 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c538 stream = &params->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()