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/linux/tools/memory-model/Documentation/
H A Dcontrol-dependencies.txt11 One such challenge is that control dependencies order only later stores.
31 However, stores are not speculated. This means that ordering is
43 the compiler might fuse the store to "b" with other stores. Worse yet,
60 identical stores on both branches of the "if" statement as follows:
104 guaranteed only when the stores differ, for example:
212 only to the stores in the then-clause and else-clause of the "if" statement
219 (*) Control dependencies can order prior loads against later stores.
221 Not prior loads against later loads, nor prior stores against
224 stores and later loads, smp_mb().
226 (*) If both legs of the "if" statement contain identical stores to
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H A Dexplanation.txt103 device, stores it in a buffer, and sets a flag to indicate the buffer
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
141 This pattern of memory accesses, where one CPU stores values to two
198 it, as loads can obtain values only from earlier stores.
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 P0 stores 1 to buf before storing 1 to flag, since it executes
223 each CPU stores to its own shared location and then loads from the
271 W: P0 stores 1 to flag executes before
274 Z: P0 stores 1 to buf executes before
275 W: P0 stores 1 to flag.
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H A Drecipes.txt46 tearing, load/store fusing, and invented loads and stores.
207 The MP pattern has one CPU execute a pair of stores to a pair of variables
314 The smp_wmb() macro orders prior stores against later stores, and the
358 second, while another CPU loads from the second variable and then stores
479 that one CPU first stores to one variable and then loads from a second,
480 while another CPU stores to the second variable and then loads from the
/linux/tools/memory-model/litmus-tests/
H A DMP+unlocklockonceonce+fencermbonceonce.litmus6 * If two locked critical sections execute on the same CPU, stores in the
7 * first must propagate to each CPU before stores in the second do, even if
/linux/fs/romfs/
H A DKconfig20 # Select the backing stores to be supported
23 prompt "RomFS backing stores"
27 Select the backing stores to be supported.
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-yuv-planar.rst14 stores the Y components. The second plane is the chroma plane and stores the
389 ``V4L2_PIX_FMT_NV12MT_16X16`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores
390 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
394 ``V4L2_PIX_FMT_NV12MT`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores
395 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
419 ``V4L2_PIX_FMT_NV12_4L4`` stores pixels in 4x4 tiles, and stores
424 ``V4L2_PIX_FMT_NV12_16L16`` stores pixels in 16x16 tiles, and stores
429 ``V4L2_PIX_FMT_NV12_32L32`` stores pixels in 32x32 tiles, and stores
434 ``V4L2_PIX_FMT_NV12M_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores
435 pixels in 2D 8x128 tiles, and stores tiles linearly in memory.
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H A Dpixfmt-y8i.rst19 word. E.g. the R200 RealSense camera stores pixel from the left sensor
/linux/tools/testing/selftests/kvm/x86/
H A Dpmu_event_filter_test.c57 uint64_t stores; member
424 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test() local
435 pmc_results.stores = rdmsr(msr_base + 1) - stores; in masked_events_guest_test()
623 bool_eq(pmc_results.stores, test->flags & ALLOW_STORES) && in run_masked_events_tests()
627 test->msg, pmc_results.loads, pmc_results.stores, in run_masked_events_tests()
/linux/Documentation/devicetree/bindings/mfd/
H A D88pm860x.txt13 - marvell,88pm860x-slave-addr: 88pm860x are two chips solution. <reg> stores the I2C address
14 of one chip, and this property stores the I2C address of
/linux/Documentation/ABI/testing/
H A Dsysfs-class-devfreq78 The /sys/class/devfreq/.../min_freq shows and stores
87 The /sys/class/devfreq/.../max_freq shows and stores
124 This ABI shows and stores the kind of work timer by users.
H A Dsysfs-class-extcon35 The /sys/class/extcon/.../state shows and stores the cable
79 The /sys/class/extcon/.../cable.X/state shows and stores the
/linux/Documentation/leds/
H A Dledtrig-transient.rst121 echo n > duration stores timer value to be used upon next
124 echo 0 > duration stores timer value to be used upon next
127 echo 1 > state stores desired transient state LED_FULL to be
129 echo 0 > state stores desired transient state LED_OFF to be
/linux/Documentation/
H A Dmemory-barriers.txt176 Furthermore, the stores committed by a CPU to the memory system may not be
177 perceived by the loads made by another CPU in the same order as the stores were
246 (*) Overlapping loads and stores within a particular CPU will appear to be
263 (Loads and stores overlap if they are targeted at overlapping pieces of
274 (*) It _must_not_ be assumed that independent loads and stores will be issued
386 A write barrier is a partial ordering on stores only; it is not required
390 memory system as time progresses. All stores _before_ a write barrier
391 will occur _before_ all the stores after the write barrier.
412 loads only; it is not required to have any effect on stores, independent
416 committing sequences of stores to the memory system that the CPU being
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/linux/tools/perf/Documentation/
H A Dperf-c2c.txt167 cpu/mem-stores/P
176 cpu/mem-stores/
227 Total stores
300 Node{cpus %hitms %stores} (Display with HITM types)
301 Node{cpus %peers %stores} (Display with peer type)
/linux/arch/sparc/lib/
H A DM7memset.S167 ! Use long word stores.
179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores.
187 ! initial cache-clearing stores
/linux/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c1418 MIPS_R2_STATS(stores); in mipsr2_decoder()
1488 MIPS_R2_STATS(stores); in mipsr2_decoder()
1845 MIPS_R2_STATS(stores); in mipsr2_decoder()
1963 MIPS_R2_STATS(stores); in mipsr2_decoder()
2270 (unsigned long)__this_cpu_read(mipsr2emustats.stores), in mipsr2_emul_show()
2271 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); in mipsr2_emul_show()
2326 __this_cpu_write((mipsr2emustats).stores, 0); in mipsr2_clear_show()
2327 __this_cpu_write((mipsr2bdemustats).stores, 0); in mipsr2_clear_show()
/linux/arch/sparc/kernel/
H A Ddtlb_prot.S20 membar #Sync ! Synchronize stores
/linux/Documentation/litmus-tests/rcu/
H A DRCU+sync+read.litmus7 * sees all stores done in prior RCU read-side critical sections. Such
/linux/arch/mips/include/asm/
H A Dmips-r2-to-r6-emul.h23 u64 stores; member
H A Dfpu_emulator.h27 unsigned long stores; member
/linux/drivers/nvmem/layouts/
H A DKconfig34 U-Boot stores its setup as environment variables. This driver adds
/linux/Documentation/translations/sp_SP/
H A Dmemory-barriers.txt194 Además, los stores asignados por una CPU al sistema de memoria pueden no
263 (*) Los loads y stores superpuestos dentro de una CPU en particular
281 (Los loads y stores se superponen si están destinados a piezas
292 (*) _No_debe_ suponerse que se emitirán loads y stores independientes
410 Una barrera de escritura es un orden parcial solo en los stores; No
415 stores _antes_ de una barrera de escritura ocurrirán _antes_ de todos
416 los stores después de la barrera de escritura.
436 ningún efecto en los stores, ya sean cargas de memoria o cargas
440 secuencias de stores en el sistema de memoria que la considerada CPU
443 si esa carga toca alguna secuencia de stores de otra CPU, entonces
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/linux/arch/powerpc/lib/
H A Dmemcpy_64.S115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_64.S115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dakebono.txt36 The Akebono board stores some board information such as the revision

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