| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_policy.c | 89 while (net_bw_of_new_state > calculate_net_bw_in_mbytes_sec(socbb, &table->state_array[index])) { in insert_entry_into_table_sorted()
96 table->state_array[i] = table->state_array[i - 1]; in insert_entry_into_table_sorted()
101 table->state_array[index] = *entry; in insert_entry_into_table_sorted()
102 table->state_array[index].dcfclk_mhz = (int)entry->dcfclk_mhz; in insert_entry_into_table_sorted()
103 table->state_array[index].fabricclk_mhz = (int)entry->fabricclk_mhz; in insert_entry_into_table_sorted()
104 table->state_array[index].dram_speed_mts = (int)entry->dram_speed_mts; in insert_entry_into_table_sorted()
117 table->state_array[i] = table->state_array[i + 1]; in remove_entry_from_table_at_index()
119 memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st)); in remove_entry_from_table_at_index()
126 unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz; in dml2_policy_build_synthetic_soc_states()
127 unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz; in dml2_policy_build_synthetic_soc_states()
[all …]
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| H A D | dml2_translation_helper.c | 357 p->in_states->state_array[0].socclk_mhz = 620.0; in dml2_init_soc_states()
358 p->in_states->state_array[0].dscclk_mhz = 716.667; in dml2_init_soc_states()
359 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
360 p->in_states->state_array[0].phyclk_d18_mhz = 667; in dml2_init_soc_states()
361 p->in_states->state_array[0].phyclk_d32_mhz = 625; in dml2_init_soc_states()
362 p->in_states->state_array[0].dtbclk_mhz = 1564.0; in dml2_init_soc_states()
363 p->in_states->state_array[0].fabricclk_mhz = 450.0; in dml2_init_soc_states()
364 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
365 p->in_states->state_array[0].dispclk_mhz = 2150.0; in dml2_init_soc_states()
366 p->in_states->state_array[0].dppclk_mhz = 2150.0; in dml2_init_soc_states()
[all …]
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| H A D | dml2_wrapper.c | 261 …s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_laten… in calculate_lowest_supported_state_for_temp_read()
266 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate… in calculate_lowest_supported_state_for_temp_read()
282 …while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_t… in calculate_lowest_supported_state_for_temp_read()
290 …dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latenci… in calculate_lowest_supported_state_for_temp_read()
590 …out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dc… in dml2_validate_and_build_resource()
591 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()
592 …out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram… in dml2_validate_and_build_resource()
593 …out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].ph… in dml2_validate_and_build_resource()
594 …out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].so… in dml2_validate_and_build_resource()
595 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
[all …]
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| H A D | dml2_utils.c | 364 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[… in dml2_calculate_rq_and_dlg_params()
366 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array… in dml2_calculate_rq_and_dlg_params()
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| H A D | display_mode_core_structs.h | 1268 …struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size … member
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| H A D | display_mode_core.c | 10044 return (states->state_array[state_idx]); in dml_get_soc_state_bounding_box()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | trinity_dpm.c | 1688 struct _StateArray *state_array; in trinity_parse_power_table() local
1703 state_array = (struct _StateArray *) in trinity_parse_power_table()
1713 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in trinity_parse_power_table()
1718 power_state_offset = (u8 *)state_array->states; in trinity_parse_power_table()
1719 for (i = 0; i < state_array->ucNumEntries; i++) { in trinity_parse_power_table()
1756 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in trinity_parse_power_table()
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| H A D | sumo_dpm.c | 1457 struct _StateArray *state_array; in sumo_parse_power_table() local
1472 state_array = (struct _StateArray *) in sumo_parse_power_table()
1482 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in sumo_parse_power_table()
1487 power_state_offset = (u8 *)state_array->states; in sumo_parse_power_table()
1488 for (i = 0; i < state_array->ucNumEntries; i++) { in sumo_parse_power_table()
1524 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in sumo_parse_power_table()
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| H A D | kv_dpm.c | 2435 struct _StateArray *state_array; in kv_parse_power_table() local
2450 state_array = (struct _StateArray *) in kv_parse_power_table()
2460 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2465 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()
2466 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()
2501 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
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| H A D | radeon_atombios.c | 2670 struct _StateArray *state_array; in radeon_atombios_parse_power_table_6() local
2686 state_array = (struct _StateArray *) in radeon_atombios_parse_power_table_6()
2695 if (state_array->ucNumEntries == 0) in radeon_atombios_parse_power_table_6()
2697 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, in radeon_atombios_parse_power_table_6()
2702 power_state_offset = (u8 *)state_array->states; in radeon_atombios_parse_power_table_6()
2703 for (i = 0; i < state_array->ucNumEntries; i++) { in radeon_atombios_parse_power_table_6()
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| H A D | si_dpm.c | 6751 struct _StateArray *state_array; in si_parse_power_table() local
6766 state_array = (struct _StateArray *) in si_parse_power_table()
6776 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
6781 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
6782 for (i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
6817 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
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| H A D | ci_dpm.c | 5506 struct _StateArray *state_array; in ci_parse_power_table() local
5522 state_array = (struct _StateArray *) in ci_parse_power_table()
5532 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in ci_parse_power_table()
5537 power_state_offset = (u8 *)state_array->states; in ci_parse_power_table()
5539 for (i = 0; i < state_array->ucNumEntries; i++) { in ci_parse_power_table()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_dpm.c | 2700 struct _StateArray *state_array; in kv_parse_power_table() local
2717 state_array = (struct _StateArray *) in kv_parse_power_table()
2727 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2732 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()
2733 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()
2764 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
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| H A D | si_dpm.c | 7265 struct _StateArray *state_array; in si_parse_power_table() local
7282 state_array = (struct _StateArray *) in si_parse_power_table()
7292 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
7297 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
7298 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
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