Searched refs:stage1 (Results 1 – 6 of 6) sorted by relevance
15 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()22 out->stage1.min_clk_index_for_latency = 0; in setup_speculative_display_config_with_meta()32 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_init_function_min_clk_for_latency()41 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_test_function_min_clk_for_latency()50 if (params->display_config->stage1.min_clk_index_for_latency > 0) { in dml2_top_optimization_optimize_function_min_clk_for_latency()52 params->optimized_display_config->stage1.min_clk_index_for_latency--; in dml2_top_optimization_optimize_function_min_clk_for_latency()257 …l->mode_support_params.min_clk_index = l->next_candidate_display_cfg.stage1.min_clk_index_for_late… in dml2_top_optimization_perform_optimization_phase()296 highest_state = l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency; in dml2_top_optimization_perform_optimization_phase_1()315 l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency = lowest_state; in dml2_top_optimization_perform_optimization_phase_1()792 …l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_l… in dml2_top_soc15_check_mode_supported()[all …]
232 luo_test_stage1_fn stage1, in luo_test() argument261 stage1(luo_fd); in luo_test()
42 luo_test_stage1_fn stage1, luo_test_stage2_fn stage2);
524 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank() local529 if (stage1) { in arm_smmu_init_context_bank()545 if (stage1) { in arm_smmu_init_context_bank()565 if (stage1) { in arm_smmu_init_context_bank()579 bool stage1; in arm_smmu_write_context_bank() local589 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_write_context_bank()613 if (stage1) { in arm_smmu_write_context_bank()629 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()640 if (stage1) in arm_smmu_write_context_bank()646 if (stage1) { in arm_smmu_write_context_bank()[all …]
1880 …_config->stage3.min_clk_index_for_latency = in_out->base_display_config->stage1.min_clk_index_for_… in pmo_dcn4_fams2_init_for_pstate_support()1891 …pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn4_fams2_init_for_pstate_support()1893 …pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn4_fams2_init_for_pstate_support()
42 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()