Searched refs:sram_base (Results 1 – 8 of 8) sorted by relevance
34 static void __iomem *sram_base; variable47 u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); in meson_smp_set_cpu_ctrl()57 writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); in meson_smp_set_cpu_ctrl()73 sram_base = of_iomap(node, 0); in meson_smp_prepare_cpus()75 if (!sram_base) { in meson_smp_prepare_cpus()125 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); in meson_smp_begin_secondary_boot()139 while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) { in meson_smp_finalize_secondary_boot()148 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); in meson_smp_finalize_secondary_boot()
214 void __iomem *sram_base; in icssm_prueth_sw_fdb_tbl_init() local217 sram_base = prueth->mem[PRUETH_MEM_SHARED_RAM].va; in icssm_prueth_sw_fdb_tbl_init()219 t->index_a = sram_base + V2_1_FDB_TBL_OFFSET; in icssm_prueth_sw_fdb_tbl_init()220 t->mac_tbl_a = sram_base + FDB_MAC_TBL_OFFSET; in icssm_prueth_sw_fdb_tbl_init()221 t->port1_stp_cfg = sram_base + FDB_PORT1_STP_CFG_OFFSET; in icssm_prueth_sw_fdb_tbl_init()222 t->port2_stp_cfg = sram_base + FDB_PORT2_STP_CFG_OFFSET; in icssm_prueth_sw_fdb_tbl_init()223 t->flood_enable_flags = sram_base + FDB_FLOOD_ENABLE_FLAGS_OFFSET; in icssm_prueth_sw_fdb_tbl_init()224 t->locks = sram_base + FDB_LOCKS_OFFSET; in icssm_prueth_sw_fdb_tbl_init()
173 void __iomem *sram_base = prueth->mem[PRUETH_MEM_SHARED_RAM].va; in icssm_prueth_hostconfig() local177 sram = sram_base + HOST_QUEUE_SIZE_ADDR; in icssm_prueth_hostconfig()184 sram = sram_base + HOST_Q1_RX_CONTEXT_OFFSET; in icssm_prueth_hostconfig()189 sram = sram_base + HOST_QUEUE_OFFSET_ADDR; in icssm_prueth_hostconfig()196 sram = sram_base + HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR; in icssm_prueth_hostconfig()203 sram = sram_base + HOST_QUEUE_DESC_OFFSET; in icssm_prueth_hostconfig()
50 void __iomem *sram_base; member
32 ((_ndev)->sram_base + SRAM_REG_OFF((_ndev), (idx))); \149 void __iomem *sram_base; member
91 reg[i] = readl(ndev->sram_base + off + i * sizeof(u32)); in aie2_get_mgmt_chann_info()343 mbox_res.ringbuf_base = ndev->sram_base; in aie2_hw_start()550 ndev->sram_base = tbl[xdna->dev_info->sram_bar]; in aie2_init()
357 ldr r1, sram_base365 ldr r1, sram_base493 sram_base: label
16900 void __iomem *sram_base; in tg3_get_invariants() local16906 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()16908 writel(0x00000000, sram_base); in tg3_get_invariants()16909 writel(0x00000000, sram_base + 4); in tg3_get_invariants()16910 writel(0xffffffff, sram_base + 4); in tg3_get_invariants()16911 if (readl(sram_base) != 0x00000000) in tg3_get_invariants()