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Searched refs:spx5_wr (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vlan.c18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
21 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
145 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_clear()
147 spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_clear()
148 spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_clear()
177 spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
179 spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); in sparx5_update_fwd()
180 spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); in sparx5_update_fwd()
183 spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
[all …]
H A Dsparx5_vcap_impl.c200 spx5_wr(VCAP_SUPER_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
203 spx5_wr(VCAP_SUPER_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
214 spx5_wr(VCAP_ES0_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
217 spx5_wr(VCAP_ES0_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
228 spx5_wr(VCAP_ES2_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
231 spx5_wr(VCAP_ES2_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
919 spx5_wr(keystr[idx] & mskstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
921 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
927 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
939 spx5_wr(admin->cache.counter, sparx5, in sparx5_vcap_is0_cache_write()
[all …]
H A Dsparx5_main.c471 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
472 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
475 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
640 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
646 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
653 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
654 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
655 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
656 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
733 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
[all …]
H A Dsparx5_ptp.c429 spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5, in sparx5_ptp_adjfine()
431 spx5_wr((u32)(tod_inc >> 32), sparx5, in sparx5_ptp_adjfine()
465 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), in sparx5_ptp_settime64()
467 spx5_wr(lower_32_bits(ts->tv_sec), in sparx5_ptp_settime64()
469 spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); in sparx5_ptp_settime64()
547 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), in sparx5_ptp_adjtime()
630 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
638 spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5, in sparx5_ptp_init()
640 spx5_wr((u32)(tod_adj >> 32), sparx5, in sparx5_ptp_init()
649 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
H A Dsparx5_port.c91 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
587 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | in sparx5_port_max_tags_set()
772 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), in sparx5_port_pcs_low_set()
780 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | in sparx5_port_pcs_low_set()
787 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
909 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | in sparx5_port_config_low_set()
922 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | in sparx5_port_config_low_set()
1101 spx5_wr(QSYS_ATOP_ATOP_SET(atop), in sparx5_port_init()
1106 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
1128 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | in sparx5_port_init()
[all …]
H A Dsparx5_qos.c106 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
268 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5, in sparx5_lg_conf_set()
362 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) | in sparx5_shaper_conf_set()
H A Dsparx5_vcap_debugfs.c282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
433 spx5_wr(value, sparx5, EACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_es2_port_stickies()
H A Dsparx5_main.h805 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, in spx5_wr() function
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_fdma.c293 spx5_wr(0xff, sparx5, FDMA_INTR_DB_ENA); in lan969x_fdma_napi_poll()
386 spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); in lan969x_fdma_init()
387 spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); in lan969x_fdma_init()