| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_clocks.c | 42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
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| H A D | radeon_combios.c | 720 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
747 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
748 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
749 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
750 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
753 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
754 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
757 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
758 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
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| H A D | radeon_atombios.c | 1135 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1188 spll->reference_freq = in radeon_atom_get_clock_info()
1191 spll->reference_freq = in radeon_atom_get_clock_info()
1193 spll->reference_div = 0; in radeon_atom_get_clock_info()
1195 spll->pll_out_min = in radeon_atom_get_clock_info()
1197 spll->pll_out_max = in radeon_atom_get_clock_info()
1201 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1203 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1205 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1208 spll->pll_in_min = in radeon_atom_get_clock_info()
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| H A D | rv6xx_dpm.c | 163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
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| H A D | rv740_dpm.c | 130 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
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| H A D | rs780_dpm.c | 991 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1013 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
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| H A D | rv730_dpm.c | 49 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
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| H A D | rv770.c | 788 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
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| H A D | r600.c | 200 return rdev->clock.spll.reference_freq; in r600_get_xclk()
227 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
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| H A D | rv770_dpm.c | 502 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
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| H A D | si_dpm.c | 4733 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
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| /linux/drivers/clk/microchip/ |
| H A D | clk-core.c | 735 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
739 if (!spll) in pic32_spll_clk_register()
742 spll->core = core; in pic32_spll_clk_register()
743 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
744 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
745 spll->status_reg = data->status_reg + core->iobase; in pic32_spll_clk_register()
746 spll->lock_mask = data->lock_mask; in pic32_spll_clk_register()
749 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; in pic32_spll_clk_register()
750 spll->idiv += 1; in pic32_spll_clk_register()
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nv40.c | 36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
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| H A D | nv50.c | 475 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
482 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
484 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
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| /linux/drivers/clk/imx/ |
| H A D | clk-imx31.c | 39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3576.dtsi | 67 spll: clock-spll { label
71 clock-output-names = "spll";
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| H A D | rk3588-base.dtsi | 406 spll: clock-0 { label
409 clock-output-names = "spll";
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc15.c | 347 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
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| H A D | amdgpu.h | 434 struct amdgpu_pll spll; member
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.c | 5327 u32 reference_clock = adev->clock.spll.reference_freq; in si_calculate_sclk_params()
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