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Searched refs:spll (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
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H A Dradeon_atombios.c1135 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1188 spll->reference_freq = in radeon_atom_get_clock_info()
1191 spll->reference_freq = in radeon_atom_get_clock_info()
1193 spll->reference_div = 0; in radeon_atom_get_clock_info()
1195 spll->pll_out_min = in radeon_atom_get_clock_info()
1197 spll->pll_out_max = in radeon_atom_get_clock_info()
1201 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1203 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1205 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1208 spll->pll_in_min = in radeon_atom_get_clock_info()
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H A Drv740_dpm.c130 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
H A Drv6xx_dpm.c163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
H A Drs780_dpm.c990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
H A Drv730_dpm.c49 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
H A Drv770.c788 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
H A Dci_dpm.c1948 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
2967 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3126 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
H A Dr600.c200 return rdev->clock.spll.reference_freq; in r600_get_xclk()
227 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
H A Drv770_dpm.c502 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
H A Dni_dpm.c2012 u32 reference_clock = rdev->clock.spll.reference_freq; in ni_calculate_sclk_params()
H A Dsi_dpm.c4740 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
/linux/drivers/clk/microchip/
H A Dclk-pic32.c733 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
736 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
737 if (!spll) in pic32_spll_clk_register()
740 spll->core = core; in pic32_spll_clk_register()
741 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
742 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
743 spll->status_reg = data->status_reg + core->iobase; in pic32_spll_clk_register()
744 spll->lock_mask = data->lock_mask; in pic32_spll_clk_register()
747 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; in pic32_spll_clk_register()
748 spll->idiv += 1; in pic32_spll_clk_register()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
H A Dnv50.c475 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
482 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
484 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c153 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1477 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5344 u32 reference_clock = adev->clock.spll.reference_freq; in si_calculate_sclk_params()