Searched refs:smu_wm_set (Results 1 – 7 of 7) sorted by relevance
487 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; in dcn31_notify_wm_ranges()492 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()500 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()502 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges()702 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( in dcn31_clk_mgr_construct()706 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()708 if (!clk_mgr->smu_wm_set.wm_set) { in dcn31_clk_mgr_construct()709 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn31_clk_mgr_construct()710 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()712 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn31_clk_mgr_construct()[all …]
39 struct dcn31_smu_watermark_set smu_wm_set; member
558 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; in dcn314_notify_wm_ranges()563 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) in dcn314_notify_wm_ranges()571 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); in dcn314_notify_wm_ranges()573 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); in dcn314_notify_wm_ranges()819 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( in dcn314_clk_mgr_construct()823 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn314_clk_mgr_construct()825 if (!clk_mgr->smu_wm_set.wm_set) { in dcn314_clk_mgr_construct()826 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn314_clk_mgr_construct()827 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()829 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn314_clk_mgr_construct()[all …]
39 struct dcn316_smu_watermark_set smu_wm_set; member
42 struct smu_watermark_set smu_wm_set; member
944 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set; in dcn35_notify_wm_ranges()949 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0) in dcn35_notify_wm_ranges()957 clk_mgr_dcn35->smu_wm_set.mc_address.high_part); in dcn35_notify_wm_ranges()959 clk_mgr_dcn35->smu_wm_set.mc_address.low_part); in dcn35_notify_wm_ranges()1447 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem( in dcn35_clk_mgr_construct()1451 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn35_clk_mgr_construct()1453 if (!clk_mgr->smu_wm_set.wm_set) { in dcn35_clk_mgr_construct()1454 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn35_clk_mgr_construct()1455 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn35_clk_mgr_construct()1457 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn35_clk_mgr_construct()[all …]
46 struct dcn35_smu_watermark_set smu_wm_set; member