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Searched refs:smc_state (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dni_dpm.c2300 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_smc_sp() argument
2307 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in ni_populate_smc_sp()
2309 smc_state->levels[ps->performance_level_count - 1].bSP = in ni_populate_smc_sp()
2396 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_smc_t() argument
2411 smc_state->levels[0].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2415 smc_state->levels[0].aT = cpu_to_be32(0); in ni_populate_smc_t()
2440 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; in ni_populate_smc_t()
2442 smc_state->levels[i].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2448 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2456 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_power_containment_values() argument
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H A Dsi_dpm.c2224 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_power_containment_values() argument
2247 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2252 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2253 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2254 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2255 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2256 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2306 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2307 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2308 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
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H A Drv770_dpm.c259 RV770_SMC_SWSTATE *smc_state) in rv770_populate_smc_t() argument
291 smc_state->levels[i].aT = cpu_to_be32(a_t); in rv770_populate_smc_t()
297 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = in rv770_populate_smc_t()
305 RV770_SMC_SWSTATE *smc_state) in rv770_populate_smc_sp() argument
311 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_sp()
313 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = in rv770_populate_smc_sp()
677 RV770_SMC_SWSTATE *smc_state) in rv770_convert_power_state_to_smc() argument
683 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in rv770_convert_power_state_to_smc()
687 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
694 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
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H A Dcypress_dpm.c767 RV770_SMC_SWSTATE *smc_state) in cypress_convert_power_state_to_smc() argument
774 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in cypress_convert_power_state_to_smc()
778 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
785 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
792 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
797 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
798 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
799 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
802 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
803 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
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H A Drv770_dpm.h231 RV770_SMC_SWSTATE *smc_state);
234 RV770_SMC_SWSTATE *smc_state);
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2394 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_power_containment_values() argument
2417 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2422 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2423 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2424 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2425 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2426 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2475 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); in si_populate_power_containment_values()
2476 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2477 smc_state in si_populate_power_containment_values()
2487 si_populate_sq_ramping_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state) si_populate_sq_ramping_values() argument
5507 si_populate_smc_sp(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state) si_populate_smc_sp() argument
5627 si_populate_smc_t(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state) si_populate_smc_t() argument
5726 si_convert_power_state_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state) si_convert_power_state_to_smc() argument
5812 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; si_upload_sw_state() local
5834 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; si_upload_ulv_state() local
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/linux/net/smc/
H A Dsmc.h79 enum smc_state { /* possible states of an SMC socket */ enum