| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | rc_calc.c | 47 int slice_width = pps->slice_width; in calc_rc_params() local
60 slice_width, slice_height, in calc_rc_params()
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| H A D | rc_calc_dpi.c | 34 to->slice_width = from->slice_width; in copy_pps_fields()
115 (uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)), in dscc_compute_dsc_parameters()
116 (uint32_t)dsc_cfg.slice_width)); /* Round-up */ in dscc_compute_dsc_parameters()
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| H A D | dc_dsc.c | 1056 int slice_width; in setup_dsc_config() local
1232 slice_width = pic_width / num_slices_h; in setup_dsc_config()
1234 is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width; in setup_dsc_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dsc/ |
| H A D | rc_calc_fpu.c | 170 int slice_width, in _do_calc_rc_params() argument
217 slice_width /= 2; in _do_calc_rc_params()
219 …padding_pixels = ((slice_width % 3) != 0) ? (3 - (slice_width % 3)) * (rc->initial_xmit_delay / sl… in _do_calc_rc_params()
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| H A D | rc_calc_fpu.h | 86 int slice_width,
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| /linux/include/drm/display/ |
| H A D | drm_dsc.h | 95 u16 slice_width; member
355 __be16 slice_width; member
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_vdsc.c | 299 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) in intel_dsc_slice_dimensions_valid()
302 if (vdsc_cfg->slice_width % 2) in intel_dsc_slice_dimensions_valid()
308 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) in intel_dsc_slice_dimensions_valid()
333 vdsc_cfg->slice_width = in intel_dsc_compute_params()
570 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
615 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
1007 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
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| H A D | intel_vdsc_regs.h | 115 #define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width) argument
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| H A D | intel_dp.c | 4286 int num_slices, int slice_width) in intel_dp_pcon_dsc_enc_bpp() argument
4296 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, in intel_dp_pcon_dsc_enc_bpp()
4310 int slice_width; in intel_dp_pcon_dsc_configure() local
4338 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, in intel_dp_pcon_dsc_configure()
4342 num_slices, slice_width); in intel_dp_pcon_dsc_configure()
4348 pps_param[2] = slice_width & 0xFF; in intel_dp_pcon_dsc_configure()
4349 pps_param[3] = slice_width >> 8; in intel_dp_pcon_dsc_configure()
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| H A D | icl_dsi.c | 1646 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
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| H A D | intel_display.c | 5451 PIPE_CONF_CHECK_I(dsc.config.slice_width); in intel_pipe_config_compare()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 306 DC_LOG_DSC("\tslice_width %d", pps->slice_width); in dsc_log_pps()
418 …dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.n… in dsc_prepare_config()
453 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; in dsc_prepare_config()
547 reg_vals->pps.slice_width = 0; in dsc_init_reg_values()
656 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/ |
| H A D | dml2_top_soc15.c | 401 unsigned int i, slice_width; in find_shift_for_valid_cache_id_assignment() local
406 slice_width = mcache_boundaries[i]; in find_shift_for_valid_cache_id_assignment()
408 slice_width = mcache_boundaries[i] - mcache_boundaries[i - 1]; in find_shift_for_valid_cache_id_assignment()
410 if (max_shift > (int)slice_width) { in find_shift_for_valid_cache_id_assignment()
411 max_shift = slice_width; in find_shift_for_valid_cache_id_assignment()
477 int i, slice_width; in calculate_h_split_for_scaling_transform() local
485 slice_width = full_vp_width / num_pipes; in calculate_h_split_for_scaling_transform()
487 pipe_vp_x_start[i] = i * slice_width; in calculate_h_split_for_scaling_transform()
488 pipe_vp_x_end[i] = (i + 1) * slice_width - 1; in calculate_h_split_for_scaling_transform()
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| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-novatek-nt37801.c | 295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder.c | 1972 soft_slice_per_enc = enc_ip_width / dsc->slice_width; in dpu_encoder_dsc_initial_line_calc()
1988 return DIV_ROUND_UP(total_pixels, dsc->slice_width); in dpu_encoder_dsc_initial_line_calc()
2052 this_frame_slices = pic_width / dsc->slice_width; in dpu_encoder_prep_dsc()
2053 intf_ip_w = this_frame_slices * dsc->slice_width; in dpu_encoder_prep_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 275 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 633 DC_LOG_DSC("\tslice_width %d", config->slice_width); in dsc_optc_config_log()
736 dsc_optc_cfg.slice_width); in link_set_dsc_on_stream()
747 dsc_optc_cfg.slice_width); in link_set_dsc_on_stream()
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| /linux/drivers/gpu/drm/msm/dsi/ |
| H A D | dsi_host.c | 2605 if (pic_width % dsc->slice_width) { in msm_dsi_host_check_dsc()
2607 pic_width, dsc->slice_width); in msm_dsi_host_check_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2307 uint32_t slice_width = 0; in hwss_tg_set_dsc_config() local
2314 slice_width = dsc_optc_cfg->slice_width; in hwss_tg_set_dsc_config()
2321 tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width); in hwss_tg_set_dsc_config()
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