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Searched refs:simd (Results 1 – 12 of 12) sorted by relevance

/linux/arch/loongarch/kernel/
H A Dcpu-probe.c57 static unsigned int simd = -1U; variable
61 get_option(&str, &simd); in cpu_setup_simd()
62 pr_info("Set SIMD width = %u\n", simd); in cpu_setup_simd()
73 if (simd < 128) { in cpu_final_simd()
78 if (simd < 256) { in cpu_final_simd()
83 simd = 0; in cpu_final_simd()
86 simd = 128; in cpu_final_simd()
89 simd = 256; in cpu_final_simd()
91 pr_info("Final SIMD width = %u\n", simd); in cpu_final_simd()
194 if ((config & CPUCFG2_LSX) && (simd >= 128)) { in cpu_probe_common()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Dgfx_v9_4_3.c715 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t … in wave_read_ind() argument
719 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
725 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in wave_read_regs() argument
731 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
741 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
746 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
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H A Damdgpu_debugfs.c452 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
457 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data); in amdgpu_debugfs_gprwave_read()
460 adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data); in amdgpu_debugfs_gprwave_read()
1179 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read()
1190 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
1210 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1270 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read()
1281 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1303 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1306 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wav in amdgpu_debugfs_gpr_read()
1164 uint32_t offset, se, sh, cu, wave, simd, data[32]; amdgpu_debugfs_wave_read() local
1255 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; amdgpu_debugfs_gpr_read() local
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H A Dgfx_v8_0.c5066 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5070 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5076 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5082 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5091 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5096 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5097 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
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H A Dgfx_v9_0.c1930 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1934 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1940 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
1946 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
1955 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1960 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1961 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1962 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1963 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
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H A Dgfx_v12_1.c778 uint32_t simd, uint32_t wave, in gfx_v12_1_read_wave_data() argument
784 WARN_ON(simd != 0); in gfx_v12_1_read_wave_data()
814 uint32_t xcc_id, uint32_t simd, in gfx_v12_1_read_wave_sgprs() argument
818 WARN_ON(simd != 0); in gfx_v12_1_read_wave_sgprs()
826 uint32_t xcc_id, uint32_t simd, in gfx_v12_1_read_wave_vgprs() argument
H A Dgfx_v12_0.c847 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
853 WARN_ON(simd != 0); in gfx_v12_0_read_wave_data()
883 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
887 WARN_ON(simd != 0); in gfx_v12_0_read_wave_sgprs()
895 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
H A Dgfx_v11_0.c1016 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) in gfx_v11_0_read_wave_data() argument
1021 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
1042 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1046 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1053 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
H A Dgfx_v10_0.c4498 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v10_0_read_wave_data() argument
4504 WARN_ON(simd != 0); in gfx_v10_0_read_wave_data()
4526 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4530 WARN_ON(simd != 0); in gfx_v10_0_read_wave_sgprs()
4537 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
/linux/tools/perf/Documentation/
H A Dperf-report.txt139 - simd: Flags describing a SIMD operation. The architecture type can be Arm's
/linux/rust/zerocopy/src/
H A Dimpls.rs1291 mod simd { module