| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_pt_walk.h | 36 const u64 *shifts; member
108 u64 pt_size = 1ull << walk->shifts[level]; in xe_pt_covers()
128 u64 pt_size = 1ull << walk->shifts[level]; in xe_pt_num_entries()
131 walk->shifts[level]; in xe_pt_num_entries()
147 addr &= ((1ull << walk->shifts[level + 1]) - 1); in xe_pt_offset()
149 return addr >> walk->shifts[level]; in xe_pt_offset()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
196 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap()
198 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap()
281 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
283 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
328 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
330 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
332 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
334 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp_cm.c | 173 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
175 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
178 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
180 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
182 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
184 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
187 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
189 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
191 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
193 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| H A D | dcn30_dwb_cm.c | 52 reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
54 reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
57 reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
59 reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
61 reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
63 reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
66 reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
68 reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
70 reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
72 reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.c | 164 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_output_csc()
166 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_output_csc()
222 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
224 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
250 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
252 reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
254 reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
256 reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
258 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
260 reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/ |
| H A D | dcn301_hubbub.c | 38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
79 hubbub3->shifts = hubbub_shift; in hubbub301_construct()
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| /linux/drivers/net/dsa/microchip/ |
| H A D | ksz8.c | 539 const u8 *shifts; in ksz8_r_dyn_mac_table() local
548 shifts = dev->info->shifts; in ksz8_r_dyn_mac_table()
577 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; in ksz8_r_dyn_mac_table()
579 shifts[DYNAMIC_MAC_ENTRIES]; in ksz8_r_dyn_mac_table()
583 shifts[DYNAMIC_MAC_FID]; in ksz8_r_dyn_mac_table()
585 shifts[DYNAMIC_MAC_SRC_PORT]; in ksz8_r_dyn_mac_table()
605 const u8 *shifts; in ksz8_r_sta_mac_table() local
610 shifts = dev->info->shifts; in ksz8_r_sta_mac_table()
634 shifts[STATIC_MAC_FWD_PORTS]; in ksz8_r_sta_mac_table()
646 shifts[STATIC_MAC_FID]; in ksz8_r_sta_mac_table()
[all …]
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| H A D | ksz9477.c | 920 const u8 *shifts; in ksz9477_mdb_add() local
927 shifts = dev->info->shifts; in ksz9477_mdb_add()
938 data = (index << shifts[ALU_STAT_INDEX]) | in ksz9477_mdb_add()
983 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; in ksz9477_mdb_add()
999 const u8 *shifts; in ksz9477_mdb_del() local
1006 shifts = dev->info->shifts; in ksz9477_mdb_del()
1017 data = (index << shifts[ALU_STAT_INDEX]) | in ksz9477_mdb_del()
1060 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; in ksz9477_mdb_del()
1388 dev->info->shifts[ALU_STAT_INDEX]; in ksz9477_enable_stp_addr()
1442 dev->info->shifts[ALU_STAT_INDEX]; in ksz9477_enable_stp_addr()
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| H A D | dcn201_hubbub.c | 41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
102 hubbub->shifts = hubbub_shift; in hubbub201_construct()
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| /linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 108 } shifts; member
127 .shifts = { \
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; in jh7110_pll_regvals_get()
286 ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd; in jh7110_pll_regvals_get()
289 ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv; in jh7110_pll_regvals_get()
380 (u32)val->mode << info->shifts.dacpd); in jh7110_pll_set_rate()
382 (u32)val->mode << info->shifts.dsmpd); in jh7110_pll_set_rate()
386 val->fbdiv << info->shifts.fbdiv); in jh7110_pll_set_rate()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_i2c_hw.h | 301 const struct dce_i2c_shift *shifts; member
310 const struct dce_i2c_shift *shifts,
318 const struct dce_i2c_shift *shifts,
326 const struct dce_i2c_shift *shifts,
334 const struct dce_i2c_shift *shifts,
342 const struct dce_i2c_shift *shifts,
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| H A D | dce_audio.h | 143 const struct dce_audio_shift *shifts; member
151 const struct dce_audio_shift *shifts,
159 const struct dce_audio_shift *shifts,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp_cm.c | 189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
250 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in read_gamut_remap()
252 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in read_gamut_remap()
339 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
341 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
417 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
419 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
421 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
423 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 156 generic->shifts = &generic_shift[en]; in define_generic_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
191 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 164 generic->shifts = &generic_shift[en]; in define_generic_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
199 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_cm_common.h | 70 struct xfer_func_shift shifts; member
85 struct cm_color_matrix_shift shifts; member
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_factory_dcn32.c | 197 generic->shifts = &generic_shift[en]; in define_generic_registers()
222 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
232 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_factory_dcn30.c | 193 generic->shifts = &generic_shift[en]; in define_generic_registers()
218 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
228 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_factory_dcn315.c | 185 generic->shifts = &generic_shift[en]; in define_generic_registers()
210 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
220 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 201 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
211 hpd->shifts = &hpd_shift; in define_hpd_registers()
221 generic->shifts = &generic_shift[en]; in define_generic_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| H A D | hw_factory_dcn401.c | 189 generic->shifts = &generic_shift[en]; in define_generic_registers()
214 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
224 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| H A D | hw_factory_dce110.c | 132 ddc->shifts = &ddc_shift; in define_ddc_registers()
142 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| H A D | hw_factory_dce80.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| H A D | hw_factory_dce60.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 149 ddc->shifts = &ddc_shift; in define_ddc_registers()
159 hpd->shifts = &hpd_shift; in define_hpd_registers()
|