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Searched refs:shared_dpll (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c120 struct intel_shared_dpll_state *shared_dpll) in intel_atomic_duplicate_dpll_state() argument
127 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
141 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
144 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
257 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
303 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
363 struct intel_shared_dpll_state *shared_dpll; in intel_find_shared_dpll() local
367 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
379 if (shared_dpll[pll->index].pipe_mask == 0) { in intel_find_shared_dpll()
386 &shared_dpll[pll->index].hw_state, in intel_find_shared_dpll()
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H A Dintel_pch_display.c256 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
387 if (crtc_state->shared_dpll == in ilk_pch_enable()
530 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); in ilk_pch_get_config()
531 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
H A Dintel_modeset_setup.c93 if (crtc_state->shared_dpll) in intel_crtc_disable_noatomic_begin()
95 crtc_state->shared_dpll, in intel_crtc_disable_noatomic_begin()
96 &crtc_state->shared_dpll->state); in intel_crtc_disable_noatomic_begin()
579 crtc_state->shared_dpll && in has_bogus_dpll_config()
H A Dintel_ddi.c269 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1535 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1579 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1623 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1689 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1733 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1776 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1884 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1952 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
4070 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
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H A Dintel_display_types.h579 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; member
1057 struct intel_shared_dpll *shared_dpll; member
H A Dintel_display.c1462 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; in intel_encoders_update_prepare()
1806 if (pipe_crtc_state->shared_dpll) in hsw_crtc_enable()
2152 if (crtc_state->shared_dpll) in get_crtc_power_domains()
3169 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
3550 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
4122 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
4835 saved_state->shared_dpll = secondary_crtc_state->shared_dpll; in copy_joiner_crtc_state_modeset()
4898 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
5671 PIPE_CONF_CHECK_P(shared_dpll); in intel_pipe_config_compare()
H A Dintel_lvds.c250 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); in intel_pre_enable_lvds()
H A Dintel_fdi.c924 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); in hsw_fdi_link_train()
H A Dintel_dpll.c1785 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1787 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
H A Dicl_dsi.c663 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()