Home
last modified time | relevance | path

Searched refs:sh_num (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc21.c310 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register() argument
315 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
316 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
320 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
328 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
331 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
340 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
356 se_num, sh_num, reg_offset); in soc21_read_register()
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Damdgpu_kms.c879 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
894 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
895 sh_num = 0xffffffff; in amdgpu_info_ioctl()
896 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
912 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Dgfx_v6_0.c1305 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
1314 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1319 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1320 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1324 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
H A Dgfx_v12_1.c82 u32 sh_num, u32 instance, int xcc_id);
1306 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_1_xcc_select_se_sh() argument
1323 if (sh_num == 0xffffffff) in gfx_v12_1_xcc_select_se_sh()
1327 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_1_xcc_select_se_sh()
H A Dgfx_v12_0.c278 u32 sh_num, u32 instance, int xcc_id);
1668 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
1685 if (sh_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1689 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_0_select_se_sh()
H A Dgfx_v11_0.c340 u32 sh_num, u32 instance, int xcc_id);
1979 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
1996 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
2000 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
H A Dgfx_v9_0.c2502 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2517 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2520 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()