| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc21.c | 311 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register()
314 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_read_indexed_register()
323 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_indexed_register()
339 se_num, sh_num, reg_offset); in soc21_read_register()
310 soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset) soc21_read_indexed_register() argument
328 soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) soc21_get_register_value() argument
340 soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) soc21_read_register() argument
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| H A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| H A D | amdgpu_kms.c | 879 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
894 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
895 sh_num = 0xffffffff; in amdgpu_info_ioctl()
896 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
912 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
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| H A D | gfx_v6_0.c | 1305 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
1314 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1319 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1320 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1324 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
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| H A D | gfx_v12_1.c | 82 u32 sh_num, u32 instance, int xcc_id);
1331 u32 sh_num, u32 instance, int xcc_id)
1348 if (sh_num == 0xffffffff) in gfx_v12_1_get_sa_active_bitmap()
1352 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_1_get_rb_active_bitmap()
1306 gfx_v12_1_xcc_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v12_1_xcc_select_se_sh() argument
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| H A D | amdgpu.h | 571 u32 sh_num, u32 reg_offset, u32 *value);
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| H A D | gfx_v12_0.c | 278 u32 sh_num, u32 instance, int xcc_id);
1675 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
1692 if (sh_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1696 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_0_select_se_sh()
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| H A D | gfx_v11_0.c | 344 u32 sh_num, u32 instance, int xcc_id);
1985 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh()
2002 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
2006 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_get_sa_active_bitmap()
1979 gfx_v11_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v11_0_select_se_sh() argument
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| H A D | gfx_v9_0.c | 2502 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2517 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2520 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
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