| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 258 struct block_sequence_state *seq_state) in dcn50_update_dchubp_dpp_sequence() argument
273 hwss_add_dpp_dppclk_control(seq_state, dpp, false, true); in dcn50_update_dchubp_dpp_sequence()
277 hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn50_update_dchubp_dpp_sequence()
281 hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst); in dcn50_update_dchubp_dpp_sequence()
285 hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs, in dcn50_update_dchubp_dpp_sequence()
288 hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs, in dcn50_update_dchubp_dpp_sequence()
295 hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req); in dcn50_update_dchubp_dpp_sequence()
300 hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs); in dcn50_update_dchubp_dpp_sequence()
302 hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); in dcn50_update_dchubp_dpp_sequence()
312 hwss_add_dpp_setup_dpp(seq_state, pipe_ctx); in dcn50_update_dchubp_dpp_sequence()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 886 struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps }; in dcn60_build_hubbub_perfmon_sequence() local
895 hwss_add_hubbub_perfmon_reset(&seq_state, hubbub); in dcn60_build_hubbub_perfmon_sequence()
921 hwss_add_hubbub_perfmon_reset(&seq_state, hubbub); in dcn60_build_hubbub_perfmon_sequence()
922 hwss_add_hubbub_perfmon_arm_out_of_order_bw(&seq_state, hubbub); in dcn60_build_hubbub_perfmon_sequence()
923 hwss_add_tg_wait_for_state(&seq_state, ref_tg, CRTC_STATE_VACTIVE); in dcn60_build_hubbub_perfmon_sequence()
924 hwss_add_tg_wait_for_state(&seq_state, ref_tg, CRTC_STATE_VBLANK); in dcn60_build_hubbub_perfmon_sequence()
925 hwss_add_hubbub_perfmon_start_out_of_order_bw(&seq_state, hubbub); in dcn60_build_hubbub_perfmon_sequence()
926 hwss_add_tg_wait_for_state(&seq_state, ref_tg, CRTC_STATE_VACTIVE); in dcn60_build_hubbub_perfmon_sequence()
927 hwss_add_hubbub_perfmon_get_out_of_order_bw(&seq_state, hubbub, in dcn60_build_hubbub_perfmon_sequence()
938 hwss_add_hubbub_perfmon_reset(&seq_state, hubbub); in dcn60_build_hubbub_perfmon_sequence()
[all …]
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| /linux/arch/mips/kernel/ |
| H A D | smp-cps.c | 46 u32 stat, seq_state; in power_up_other_cluster() local
54 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in power_up_other_cluster()
55 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in power_up_other_cluster()
56 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) in power_up_other_cluster()
71 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in power_up_other_cluster()
72 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in power_up_other_cluster()
73 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) in power_up_other_cluster()
472 u32 access, stat, seq_state; in boot_core() local
565 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in boot_core()
566 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in boot_core()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 3927 struct block_sequence_state *seq_state) in program_cursor_attributes_sequence() argument
3943 hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe); in program_cursor_attributes_sequence()
3945 hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true); in program_cursor_attributes_sequence()
3947 hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, true); in program_cursor_attributes_sequence()
3951 hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe); in program_cursor_attributes_sequence()
3953 hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); in program_cursor_attributes_sequence()
3955 hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe); in program_cursor_attributes_sequence()
3957 hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); in program_cursor_attributes_sequence()
3962 hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program); in program_cursor_attributes_sequence()
3964 hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false); in program_cursor_attributes_sequence()
[all …]
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| /linux/drivers/net/ieee802154/ |
| H A D | mcr20a.c | 885 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete() local
894 switch (seq_state) { in mcr20a_irq_clean_complete()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/ |
| H A D | dcn60_clk_mgr.c | 1538 struct block_sequence_state *seq_state) in dcn60_build_clock_update_for_bls() argument
1562 hwss_add_clk_mgr_update_clocks(seq_state, clk_mgr_base); in dcn60_build_clock_update_for_bls()
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 559 :File: ``seq_state`` (rw)
|