| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| H A D | soc24.c | 137 bool indexed, u32 se_num, in soc24_get_register_value() argument
141 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc24_get_register_value()
150 static int soc24_read_register(struct amdgpu_device *adev, u32 se_num, in soc24_read_register() argument
167 se_num, sh_num, reg_offset); in soc24_read_register()
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| H A D | soc21.c | 311 bool indexed, u32 se_num, in soc21_get_register_value() argument
315 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
323 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
340 se_num, sh_num, reg_offset); in soc21_read_register()
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| H A D | gfx_v12_1.c | 202 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1608 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v12_1_xcc_select_se_sh() argument
1620 if (se_num == 0xffffffff) in gfx_v12_1_xcc_select_se_sh()
1624 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_1_xcc_select_se_sh()
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| H A D | amdgpu.h | 441 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
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| H A D | gfx_v12_0.c | 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1685 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v12_0_select_se_sh() argument
1697 if (se_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1701 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_0_select_se_sh()
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| H A D | gfx_v9_0.c | 2503 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2513 if (se_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2516 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
7068 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_reset_ras_error_count()
7130 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_query_ras_error_count()
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| H A D | gfx_v9_4_3.c | 688 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_3_xcc_select_se_sh() argument
700 if (se_num == 0xffffffff) in gfx_v9_4_3_xcc_select_se_sh()
704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_3_xcc_select_se_sh()
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| H A D | gfx_v11_0.c | 351 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
2010 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v11_0_select_se_sh() argument
2022 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
2026 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()
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| H A D | gfx_v8_0.c | 3401 u32 se_num, u32 sh_num, u32 instance, in gfx_v8_0_select_se_sh() argument
3411 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3414 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
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| H A D | gfx_v10_0.c | 3685 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5058 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v10_0_select_se_sh() argument
5070 if (se_num == 0xffffffff) in gfx_v10_0_select_se_sh()
5074 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
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