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Searched refs:sclk (Results 1 – 25 of 142) sorted by relevance

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/linux/drivers/clk/
H A Dclk-scmi.c220 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, in scmi_clk_ops_init() argument
228 .num_parents = sclk->info->num_parents, in scmi_clk_ops_init()
230 .name = sclk->info->name, in scmi_clk_ops_init()
231 .parent_data = sclk->parent_data, in scmi_clk_ops_init()
234 sclk->hw.init = &init; in scmi_clk_ops_init()
235 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init()
239 if (sclk->info->rate_discrete) { in scmi_clk_ops_init()
240 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init()
245 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init()
246 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init()
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H A Dclk-scpi.c141 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
151 sclk->hw.init = &init; in scpi_clk_ops_init()
152 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
155 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
156 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
157 return PTR_ERR(sclk->info); in scpi_clk_ops_init()
159 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
165 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init()
167 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
179 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
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/linux/drivers/clk/ralink/
H A Dclk-mt7621.c134 struct mt7621_gate *sclk) in mt7621_gate_ops_init() argument
145 .parent_names = &sclk->parent_name, in mt7621_gate_ops_init()
147 .name = sclk->name, in mt7621_gate_ops_init()
150 sclk->hw.init = &init; in mt7621_gate_ops_init()
151 return devm_clk_hw_register(dev, &sclk->hw); in mt7621_gate_ops_init()
159 struct mt7621_gate *sclk; in mt7621_register_gates() local
163 sclk = &mt7621_gates[i]; in mt7621_register_gates()
164 sclk->priv = priv; in mt7621_register_gates()
165 ret = mt7621_gate_ops_init(dev, sclk); in mt7621_register_gates()
167 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_gates()
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/linux/drivers/clk/microchip/
H A Dclk-core.c774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate()
795 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
802 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate()
805 v = readl(sclk->slew_reg); in sclk_set_rate()
811 writel(v, sclk->slew_reg); in sclk_set_rate()
814 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate()
817 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate()
824 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
827 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
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H A Dgf100.c67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
102 u32 sclk, sctl, sdiv = 2; in read_div() local
112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
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H A Dgt215.c64 u32 sctl, sdiv, sclk; in read_clk() local
99 sclk = read_vco(clk, idx); in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
128 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
131 sclk = read_clk(clk, 0x10 + idx, false); in read_pll()
139 return sclk * N / MP; in read_pll()
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
207 sclk = read_vco(clk, idx); in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
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/linux/drivers/gpu/drm/radeon/
H A Drv730_dpm.c39 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
109 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
302 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
303 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
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H A Dbtc_dpm.c1214 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1218 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1224 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1231 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1233 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1234 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1244 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1247 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1250 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
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H A Drv770_dpm.c273 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
276 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
284 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
487 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
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H A Dtrinity_dpm.c536 u32 index, u32 sclk) in trinity_set_divider_value() argument
544 sclk, false, &dividers); in trinity_set_divider_value()
554 sclk/2, false, &dividers); in trinity_set_divider_value()
674 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
922 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
935 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
936 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1286 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1288 if (sclk < 20000) in trinity_calculate_vce_wm()
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H A Dkv_dpm.c376 u32 index, u32 sclk) in kv_set_divider_value() argument
383 sclk, false, &dividers); in kv_set_divider_value()
388 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
565 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
579 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1536 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1544 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1550 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1561 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
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H A Drv740_dpm.c120 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
348 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
409 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
419 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
553 pl->sclk, false, &dividers); in sumo_program_power_level()
669 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
788 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
842 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
843 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
860 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
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H A Dsi_dpm.c1694 SISLANDS_SMC_SCLK_VALUE *sclk);
2259 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2260 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2279 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2280 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2354 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2789 u32 sclk = 0; in si_init_smc_spll_table() local
2802 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2835 sclk += 512; in si_init_smc_spll_table()
2909 u32 mclk, sclk; in si_apply_state_adjust_rules() local
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/linux/sound/soc/meson/
H A Daxg-tdm-formatter.c20 struct clk *sclk; member
114 ret = clk_set_phase(formatter->sclk, invert ? 0 : 180); in axg_tdm_formatter_enable()
126 ret = clk_prepare_enable(formatter->sclk); in axg_tdm_formatter_enable()
132 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_enable()
151 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_disable()
208 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); in axg_tdm_formatter_power_up()
298 formatter->sclk = devm_clk_get(dev, "sclk"); in axg_tdm_formatter_probe()
299 if (IS_ERR(formatter->sclk)) in axg_tdm_formatter_probe()
300 return dev_err_probe(dev, PTR_ERR(formatter->sclk), "failed to get sclk\n"); in axg_tdm_formatter_probe()
409 ret = clk_prepare_enable(ts->iface->sclk); in axg_tdm_stream_set_cont_clocks()
[all …]
/linux/drivers/power/reset/
H A Dat91-poweroff.c55 struct clk *sclk; member
162 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
163 if (IS_ERR(at91_shdwc.sclk)) in at91_poweroff_probe()
164 return PTR_ERR(at91_shdwc.sclk); in at91_poweroff_probe()
166 ret = clk_prepare_enable(at91_shdwc.sclk); in at91_poweroff_probe()
201 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_probe()
213 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_remove()
H A Dat91-reset.c85 struct clk *sclk; member
377 reset->sclk = devm_clk_get(&pdev->dev, NULL); in at91_reset_probe()
378 if (IS_ERR(reset->sclk)) in at91_reset_probe()
379 return PTR_ERR(reset->sclk); in at91_reset_probe()
381 ret = clk_prepare_enable(reset->sclk); in at91_reset_probe()
415 clk_disable_unprepare(reset->sclk); in at91_reset_probe()
424 clk_disable_unprepare(reset->sclk); in at91_reset_remove()
H A Dat91-sama5d2_shdwc.c94 struct clk *sclk; member
360 at91_shdwc->sclk = devm_clk_get(&pdev->dev, NULL); in at91_shdwc_probe()
361 if (IS_ERR(at91_shdwc->sclk)) in at91_shdwc_probe()
362 return PTR_ERR(at91_shdwc->sclk); in at91_shdwc_probe()
364 ret = clk_prepare_enable(at91_shdwc->sclk); in at91_shdwc_probe()
421 clk_disable_unprepare(at91_shdwc->sclk); in at91_shdwc_probe()
441 clk_disable_unprepare(shdw->sclk); in at91_shdwc_remove()
/linux/drivers/media/dvb-frontends/
H A Dcx24110.c544 s32 afc; unsigned sclk; in cx24110_get_frontend() local
548 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend()
551 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend()
552 else if (sclk==1) sclk=60666000L; in cx24110_get_frontend()
553 else if (sclk==2) sclk=80888000L; in cx24110_get_frontend()
554 else sclk=90999000L; in cx24110_get_frontend()
555 sclk>>=8; in cx24110_get_frontend()
556 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend()
557 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend()
558 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
/linux/drivers/clocksource/
H A Dtimer-atmel-st.c185 struct clk *sclk; in atmel_st_timer_init() local
216 sclk = of_clk_get(node, 0); in atmel_st_timer_init()
217 if (IS_ERR(sclk)) { in atmel_st_timer_init()
219 return PTR_ERR(sclk); in atmel_st_timer_init()
222 ret = clk_prepare_enable(sclk); in atmel_st_timer_init()
228 sclk_rate = clk_get_rate(sclk); in atmel_st_timer_init()
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c75 struct clk *sclk; member
102 clk_prepare_enable(info->sclk); in ep93xx_i2s_enable()
147 clk_disable_unprepare(info->sclk); in ep93xx_i2s_disable()
335 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
339 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); in ep93xx_i2s_hw_params()
455 info->sclk = clk_get(&pdev->dev, "sclk"); in ep93xx_i2s_probe()
456 if (IS_ERR(info->sclk)) { in ep93xx_i2s_probe()
457 err = PTR_ERR(info->sclk); in ep93xx_i2s_probe()
483 clk_put(info->sclk); in ep93xx_i2s_probe()
495 clk_put(info->sclk); in ep93xx_i2s_remove()
/linux/Documentation/devicetree/bindings/rtc/
H A Dmoxa,moxart-rtc.txt6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
14 rtc-sclk-gpios = <&gpio 5 0>;
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c1862 SISLANDS_SMC_SCLK_VALUE *sclk);
2433 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2434 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2452 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2453 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2963 u32 sclk = 0; in si_init_smc_spll_table() local
2976 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); in si_init_smc_spll_table()
3008 sclk += 512; in si_init_smc_spll_table()
3198 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_em.c159 struct clk *sclk; in serial8250_em_probe() local
174 sclk = devm_clk_get_enabled(dev, "sclk"); in serial8250_em_probe()
175 if (IS_ERR(sclk)) in serial8250_em_probe()
176 return dev_err_probe(dev, PTR_ERR(sclk), "unable to get clock\n"); in serial8250_em_probe()
186 up.port.uartclk = clk_get_rate(sclk); in serial8250_em_probe()

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