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Searched refs:scl_data (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c192 struct scaler_data *scl_data, in dpp201_get_optimal_number_of_taps() argument
196 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps()
197 scl_data->viewport.height != scl_data->v_active && in dpp201_get_optimal_number_of_taps()
199 scl_data->format == PIXEL_FORMAT_FP16) in dpp201_get_optimal_number_of_taps()
202 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
208 if (scl_data->ratios.horz.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
209 scl_data->ratios.horz.value--; in dpp201_get_optimal_number_of_taps()
210 if (scl_data->ratios.vert.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
211 scl_data->ratios.vert.value--; in dpp201_get_optimal_number_of_taps()
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H A Ddcn201_dpp.h72 struct scaler_data scl_data; member
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c285 const struct scaler_data *scl_data, in dscl401_calc_lb_num_partitions() argument
293 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
294 scl_data->viewport.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
295 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
296 scl_data->viewport_c.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
317 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
318 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
331 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
332 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
347 if (scl_data->lb_params.alpha_en in dscl401_calc_lb_num_partitions()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1173 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1177 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1181 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1202 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1205 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1210 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1212 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1214 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
1215 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
1216 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( in calculate_scaling_ratios()
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H A Ddc_hw_sequencer.c345 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
402 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
3091 const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data; in hwss_dpp_set_scaler() local
3094 dpp->funcs->dpp_set_scaler(dpp, scl_data); in hwss_dpp_set_scaler()
3964 const struct scaler_data *scl_data) in hwss_add_dpp_set_scaler() argument
3969 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data; in hwss_add_dpp_set_scaler()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c494 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
505 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
922 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
923 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
925 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
926 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1549 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1567 &pipe_ctx->plane_res.scl_data); in program_scaler()
1768 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2662 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in set_default_colors()
2669 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in set_default_colors()
3062 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
3121 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
3122 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
3123 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
3124 pipe_ctx->plane_res.scl_data.viewport.y, in dce110_program_front_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c977 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn401_set_cursor_position()
978 .recout = pipe_ctx->plane_res.scl_data.recout, in dcn401_set_cursor_position()
979 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn401_set_cursor_position()
980 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn401_set_cursor_position()
999 if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) || in dcn401_set_cursor_position()
1000 (pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) { in dcn401_set_cursor_position()
1084 bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
1086 x_pos = pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
2810 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn401_detect_pipe_changes()
2813 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn401_detect_pipe_changes()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c274 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
275 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
276 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
277 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
H A Ddml2_translation_helper.c999 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
1007 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.h576 struct scaler_data scl_data; member
601 struct scaler_data *scl_data,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1590 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; in dcn20_populate_dml_pipes_from_context()
1660 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
1665 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.h676 struct scaler_data *scl_data,