Searched refs:saved_reg (Results 1 – 5 of 5) sorted by relevance
194 u32 saved_reg; member219 ctrl->saved_reg = readl(ctrl->base); in mvebu_clk_gating_suspend()225 writel(ctrl->saved_reg, ctrl->base); in mvebu_clk_gating_resume()
64 u32 saved_reg; member315 irqchip_data->saved_reg = readl_relaxed(data->regs + CHANIER(i)); in imx_intmux_runtime_suspend()337 writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i)); in imx_intmux_runtime_resume()
237 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) { in nv04_dfp_prepare_sel_clk()238 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1; in nv04_dfp_prepare_sel_clk()289 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()606 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals); in nv04_dfp_restore()
85 struct nv04_mode_state saved_reg; member
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()677 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; in nv_crtc_save()697 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; in nv_crtc_restore()702 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); in nv_crtc_restore()