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Searched refs:safe_to_lower (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c86 bool safe_to_lower) in dcn201_update_clocks() argument
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
126 if (should_set_clock(safe_to_lower, in dcn201_update_clocks()
130 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn201_update_clocks()
135 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn201_update_clocks()
140 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) in dcn201_update_clocks()
143 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn201_update_clocks()
151 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn201_update_clocks()
157 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { in dcn201_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c105 struct dc_state *context, bool safe_to_lower) in dcn20_update_clocks_update_dpp_dto() argument
121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn20_update_clocks_update_dpp_dto()
218 bool safe_to_lower) in dcn2_update_clocks() argument
253 if (enter_display_off == safe_to_lower) { in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
268 if (should_set_clock(safe_to_lower, in dcn2_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { in dcn2_update_clocks()
283 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn2_update_clocks()
290 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn2_update_clocks()
296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn2_update_clocks()
[all …]
H A Ddcn20_clk_mgr.h31 bool safe_to_lower);
35 bool safe_to_lower);
37 struct dc_state *context, bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
H A Ddcn401_hubbub.c71 bool safe_to_lower) in hubbub401_program_urgent_watermarks() argument
78 if (safe_to_lower || watermarks->dcn4x.a.urgent > hubbub2->watermarks.dcn4x.a.urgent) { in hubbub401_program_urgent_watermarks()
89 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_flip in hubbub401_program_urgent_watermarks()
98 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_nom in hubbub401_program_urgent_watermarks()
107 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_mall in hubbub401_program_urgent_watermarks()
115 …if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.a.refc… in hubbub401_program_urgent_watermarks()
122 …if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_meta_trip_to_mem > hubbub2->watermarks.dcn4x.a… in hubbub401_program_urgent_watermarks()
131 if (safe_to_lower || watermarks->dcn4x.b.urgent > hubbub2->watermarks.dcn4x.b.urgent) { in hubbub401_program_urgent_watermarks()
142 if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_flip in hubbub401_program_urgent_watermarks()
151 if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_nom in hubbub401_program_urgent_watermarks()
[all …]
H A Ddcn401_hubbub.h142 bool safe_to_lower);
148 bool safe_to_lower);
154 bool safe_to_lower);
160 bool safe_to_lower);
200 bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c89 bool safe_to_lower) in ramp_up_dispclk_with_dpp() argument
153 if (!safe_to_lower) in ramp_up_dispclk_with_dpp()
189 bool safe_to_lower) in rv1_update_clocks() argument
214 if (enter_display_off == safe_to_lower) { in rv1_update_clocks()
230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rv1_update_clocks()
250 if (should_set_clock(safe_to_lower, in rv1_update_clocks()
272 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) in rv1_update_clocks()
274 ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower); in rv1_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c195 bool safe_to_lower) in dcn3_update_clocks() argument
228 if (enter_display_off == safe_to_lower) in dcn3_update_clocks()
235 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
240 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
253 if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) { in dcn3_update_clocks()
259 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn3_update_clocks()
276 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn3_update_clocks()
286 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in dcn3_update_clocks()
295 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn3_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c557 struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz) in dcn401_update_clocks_update_dpp_dto() argument
584 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn401_update_clocks_update_dpp_dto()
737 params->update_dppclk_dto_params.safe_to_lower, in dcn401_execute_block_sequence()
768 bool safe_to_lower) in dcn401_build_update_bandwidth_clocks_sequence() argument
807 if (enter_display_off == safe_to_lower) { in dcn401_build_update_bandwidth_clocks_sequence()
817 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn401_build_update_bandwidth_clocks_sequence()
845 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn401_build_update_bandwidth_clocks_sequence()
857 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn401_build_update_bandwidth_clocks_sequence()
867 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn401_build_update_bandwidth_clocks_sequence()
901 …if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.pr… in dcn401_build_update_bandwidth_clocks_sequence()
[all …]
H A Ddcn401_clk_mgr.h58 bool safe_to_lower; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c190 bool safe_to_lower, bool disable) in dcn35_disable_otg_wa() argument
203 struct pipe_ctx *pipe = safe_to_lower in dcn35_disable_otg_wa()
281 struct dc_state *context, bool safe_to_lower) in dcn35_update_clocks_update_dpp_dto() argument
310 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn35_update_clocks_update_dpp_dto()
315 if (safe_to_lower) in dcn35_update_clocks_update_dpp_dto()
342 bool safe_to_lower) in dcn35_notify_host_router_bw() argument
370 …if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_ro… in dcn35_notify_host_router_bw()
379 bool safe_to_lower) in dcn35_update_clocks() argument
404 if (safe_to_lower) { in dcn35_update_clocks()
457 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn35_update_clocks()
[all …]
H A Ddcn35_clk_mgr.h54 bool safe_to_lower);
70 bool safe_to_lower,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c315 struct dc_state *context, bool safe_to_lower) in dcn32_update_clocks_update_dpp_dto() argument
342 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn32_update_clocks_update_dpp_dto()
623 bool safe_to_lower) in dcn32_update_clocks() argument
658 if (enter_display_off == safe_to_lower) in dcn32_update_clocks()
665 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn32_update_clocks()
680 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && in dcn32_update_clocks()
686 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn32_update_clocks()
692 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn32_update_clocks()
706 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn32_update_clocks()
735 …if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_pr… in dcn32_update_clocks()
[all …]
H A Ddcn32_clk_mgr.h36 struct dc_state *context, bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/
H A Ddcn201_hubbub.c57 bool safe_to_lower) in hubbub201_program_watermarks() argument
62 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
65 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c674 bool safe_to_lower) in dce_update_clocks() argument
686 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce_update_clocks()
692 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce_update_clocks()
701 bool safe_to_lower) in dce11_update_clocks() argument
713 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce11_update_clocks()
719 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce11_update_clocks()
728 bool safe_to_lower) in dce112_update_clocks() argument
740 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
746 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce112_update_clocks()
755 bool safe_to_lower) in dce12_update_clocks() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c107 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) in rn_update_clocks_update_dpp_dto() argument
124 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in rn_update_clocks_update_dpp_dto()
133 bool safe_to_lower) in rn_update_clocks() argument
152 if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) { in rn_update_clocks()
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
179 if (should_set_clock(safe_to_lower, in rn_update_clocks()
199 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in rn_update_clocks()
206 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in rn_update_clocks()
219 safe_to_lower); in rn_update_clocks()
229 safe_to_lower); in rn_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c86 bool safe_to_lower) in dce12_update_clocks() argument
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
H A Ddcn21_hubbub.h132 bool safe_to_lower);
137 bool safe_to_lower);
142 bool safe_to_lower);
147 bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/
H A Ddcn32_hubbub.h123 bool safe_to_lower);
129 bool safe_to_lower);
135 bool safe_to_lower);
141 bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c193 bool safe_to_lower) in dce112_update_clocks() argument
205 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
211 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce112_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c596 bool safe_to_lower) in hubbub2_program_watermarks() argument
604 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
607 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
617 safe_to_lower = true; in hubbub2_program_watermarks()
619 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h47 bool safe_to_lower);
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h287 bool safe_to_lower);