xref: /linux/drivers/net/wireless/realtek/rtw89/core.h (revision 9410645520e9b820069761f3450ef6661418e279)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7 
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15 
16 struct rtw89_dev;
17 struct rtw89_pci_info;
18 struct rtw89_mac_gen_def;
19 struct rtw89_phy_gen_def;
20 struct rtw89_efuse_block_cfg;
21 struct rtw89_h2c_rf_tssi;
22 struct rtw89_fw_txpwr_track_cfg;
23 struct rtw89_phy_rfk_log_fmt;
24 struct rtw89_debugfs;
25 
26 extern const struct ieee80211_ops rtw89_ops;
27 
28 #define MASKBYTE0 0xff
29 #define MASKBYTE1 0xff00
30 #define MASKBYTE2 0xff0000
31 #define MASKBYTE3 0xff000000
32 #define MASKBYTE4 0xff00000000ULL
33 #define MASKHWORD 0xffff0000
34 #define MASKLWORD 0x0000ffff
35 #define MASKDWORD 0xffffffff
36 #define RFREG_MASK 0xfffff
37 #define INV_RF_DATA 0xffffffff
38 #define BYPASS_CR_DATA 0xbabecafe
39 
40 #define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
41 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
42 #define CFO_TRACK_MAX_USER 64
43 #define MAX_RSSI 110
44 #define RSSI_FACTOR 1
45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
46 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
47 #define DELTA_SWINGIDX_SIZE 30
48 
49 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
50 #define RTW89_RADIOTAP_ROOM_EHT \
51 	(sizeof(struct ieee80211_radiotap_tlv) + \
52 	 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
53 	 sizeof(struct ieee80211_radiotap_tlv) + \
54 	 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
55 #define RTW89_RADIOTAP_ROOM \
56 	ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
57 
58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
59 #define RTW89_HTC_VARIANT_HE 3
60 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
61 #define RTW89_HTC_VARIANT_HE_CID_OM 1
62 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
63 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
64 
65 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
66 enum htc_om_channel_width {
67 	HTC_OM_CHANNEL_WIDTH_20 = 0,
68 	HTC_OM_CHANNEL_WIDTH_40 = 1,
69 	HTC_OM_CHANNEL_WIDTH_80 = 2,
70 	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
71 };
72 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
74 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
75 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
76 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
77 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
78 
79 #define RTW89_TF_PAD GENMASK(11, 0)
80 #define RTW89_TF_BASIC_USER_INFO_SZ 6
81 
82 #define RTW89_GET_TF_USER_INFO_AID12(data)	\
83 	le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
84 #define RTW89_GET_TF_USER_INFO_RUA(data)	\
85 	le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
86 #define RTW89_GET_TF_USER_INFO_UL_MCS(data)	\
87 	le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
88 
89 enum rtw89_subband {
90 	RTW89_CH_2G = 0,
91 	RTW89_CH_5G_BAND_1 = 1,
92 	/* RTW89_CH_5G_BAND_2 = 2, unused */
93 	RTW89_CH_5G_BAND_3 = 3,
94 	RTW89_CH_5G_BAND_4 = 4,
95 
96 	RTW89_CH_6G_BAND_IDX0, /* Low */
97 	RTW89_CH_6G_BAND_IDX1, /* Low */
98 	RTW89_CH_6G_BAND_IDX2, /* Mid */
99 	RTW89_CH_6G_BAND_IDX3, /* Mid */
100 	RTW89_CH_6G_BAND_IDX4, /* High */
101 	RTW89_CH_6G_BAND_IDX5, /* High */
102 	RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
103 	RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
104 
105 	RTW89_SUBBAND_NR,
106 	RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
107 };
108 
109 enum rtw89_gain_offset {
110 	RTW89_GAIN_OFFSET_2G_CCK,
111 	RTW89_GAIN_OFFSET_2G_OFDM,
112 	RTW89_GAIN_OFFSET_5G_LOW,
113 	RTW89_GAIN_OFFSET_5G_MID,
114 	RTW89_GAIN_OFFSET_5G_HIGH,
115 	RTW89_GAIN_OFFSET_6G_L0,
116 	RTW89_GAIN_OFFSET_6G_L1,
117 	RTW89_GAIN_OFFSET_6G_M0,
118 	RTW89_GAIN_OFFSET_6G_M1,
119 	RTW89_GAIN_OFFSET_6G_H0,
120 	RTW89_GAIN_OFFSET_6G_H1,
121 	RTW89_GAIN_OFFSET_6G_UH0,
122 	RTW89_GAIN_OFFSET_6G_UH1,
123 
124 	RTW89_GAIN_OFFSET_NR,
125 };
126 
127 enum rtw89_hci_type {
128 	RTW89_HCI_TYPE_PCIE,
129 	RTW89_HCI_TYPE_USB,
130 	RTW89_HCI_TYPE_SDIO,
131 };
132 
133 enum rtw89_core_chip_id {
134 	RTL8852A,
135 	RTL8852B,
136 	RTL8852BT,
137 	RTL8852C,
138 	RTL8851B,
139 	RTL8922A,
140 };
141 
142 enum rtw89_chip_gen {
143 	RTW89_CHIP_AX,
144 	RTW89_CHIP_BE,
145 
146 	RTW89_CHIP_GEN_NUM,
147 };
148 
149 enum rtw89_cv {
150 	CHIP_CAV,
151 	CHIP_CBV,
152 	CHIP_CCV,
153 	CHIP_CDV,
154 	CHIP_CEV,
155 	CHIP_CFV,
156 	CHIP_CV_MAX,
157 	CHIP_CV_INVALID = CHIP_CV_MAX,
158 };
159 
160 enum rtw89_bacam_ver {
161 	RTW89_BACAM_V0,
162 	RTW89_BACAM_V1,
163 
164 	RTW89_BACAM_V0_EXT = 99,
165 };
166 
167 enum rtw89_core_tx_type {
168 	RTW89_CORE_TX_TYPE_DATA,
169 	RTW89_CORE_TX_TYPE_MGMT,
170 	RTW89_CORE_TX_TYPE_FWCMD,
171 };
172 
173 enum rtw89_core_rx_type {
174 	RTW89_CORE_RX_TYPE_WIFI		= 0,
175 	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
176 	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
177 	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
178 	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
179 	RTW89_CORE_RX_TYPE_SS2FW	= 5,
180 	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
181 	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
182 	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
183 	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
184 	RTW89_CORE_RX_TYPE_C2H		= 10,
185 	RTW89_CORE_RX_TYPE_CSI		= 11,
186 	RTW89_CORE_RX_TYPE_CQI		= 12,
187 	RTW89_CORE_RX_TYPE_H2C		= 13,
188 	RTW89_CORE_RX_TYPE_FWDL		= 14,
189 };
190 
191 enum rtw89_txq_flags {
192 	RTW89_TXQ_F_AMPDU		= 0,
193 	RTW89_TXQ_F_BLOCK_BA		= 1,
194 	RTW89_TXQ_F_FORBID_BA		= 2,
195 };
196 
197 enum rtw89_net_type {
198 	RTW89_NET_TYPE_NO_LINK		= 0,
199 	RTW89_NET_TYPE_AD_HOC		= 1,
200 	RTW89_NET_TYPE_INFRA		= 2,
201 	RTW89_NET_TYPE_AP_MODE		= 3,
202 };
203 
204 enum rtw89_wifi_role {
205 	RTW89_WIFI_ROLE_NONE,
206 	RTW89_WIFI_ROLE_STATION,
207 	RTW89_WIFI_ROLE_AP,
208 	RTW89_WIFI_ROLE_AP_VLAN,
209 	RTW89_WIFI_ROLE_ADHOC,
210 	RTW89_WIFI_ROLE_ADHOC_MASTER,
211 	RTW89_WIFI_ROLE_MESH_POINT,
212 	RTW89_WIFI_ROLE_MONITOR,
213 	RTW89_WIFI_ROLE_P2P_DEVICE,
214 	RTW89_WIFI_ROLE_P2P_CLIENT,
215 	RTW89_WIFI_ROLE_P2P_GO,
216 	RTW89_WIFI_ROLE_NAN,
217 	RTW89_WIFI_ROLE_MLME_MAX
218 };
219 
220 enum rtw89_upd_mode {
221 	RTW89_ROLE_CREATE,
222 	RTW89_ROLE_REMOVE,
223 	RTW89_ROLE_TYPE_CHANGE,
224 	RTW89_ROLE_INFO_CHANGE,
225 	RTW89_ROLE_CON_DISCONN,
226 	RTW89_ROLE_BAND_SW,
227 	RTW89_ROLE_FW_RESTORE,
228 };
229 
230 enum rtw89_self_role {
231 	RTW89_SELF_ROLE_CLIENT,
232 	RTW89_SELF_ROLE_AP,
233 	RTW89_SELF_ROLE_AP_CLIENT
234 };
235 
236 enum rtw89_msk_sO_el {
237 	RTW89_NO_MSK,
238 	RTW89_SMA,
239 	RTW89_TMA,
240 	RTW89_BSSID
241 };
242 
243 enum rtw89_sch_tx_sel {
244 	RTW89_SCH_TX_SEL_ALL,
245 	RTW89_SCH_TX_SEL_HIQ,
246 	RTW89_SCH_TX_SEL_MG0,
247 	RTW89_SCH_TX_SEL_MACID,
248 };
249 
250 /* RTW89_ADDR_CAM_SEC_NONE	: not enabled
251  * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
252  * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
253  * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
254  */
255 enum rtw89_add_cam_sec_mode {
256 	RTW89_ADDR_CAM_SEC_NONE		= 0,
257 	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
258 	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
259 	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
260 };
261 
262 enum rtw89_sec_key_type {
263 	RTW89_SEC_KEY_TYPE_NONE		= 0,
264 	RTW89_SEC_KEY_TYPE_WEP40	= 1,
265 	RTW89_SEC_KEY_TYPE_WEP104	= 2,
266 	RTW89_SEC_KEY_TYPE_TKIP		= 3,
267 	RTW89_SEC_KEY_TYPE_WAPI		= 4,
268 	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
269 	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
270 	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
271 	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
272 	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
273 	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
274 };
275 
276 enum rtw89_port {
277 	RTW89_PORT_0 = 0,
278 	RTW89_PORT_1 = 1,
279 	RTW89_PORT_2 = 2,
280 	RTW89_PORT_3 = 3,
281 	RTW89_PORT_4 = 4,
282 	RTW89_PORT_NUM
283 };
284 
285 enum rtw89_band {
286 	RTW89_BAND_2G = 0,
287 	RTW89_BAND_5G = 1,
288 	RTW89_BAND_6G = 2,
289 	RTW89_BAND_NUM,
290 };
291 
292 enum rtw89_hw_rate {
293 	RTW89_HW_RATE_CCK1	= 0x0,
294 	RTW89_HW_RATE_CCK2	= 0x1,
295 	RTW89_HW_RATE_CCK5_5	= 0x2,
296 	RTW89_HW_RATE_CCK11	= 0x3,
297 	RTW89_HW_RATE_OFDM6	= 0x4,
298 	RTW89_HW_RATE_OFDM9	= 0x5,
299 	RTW89_HW_RATE_OFDM12	= 0x6,
300 	RTW89_HW_RATE_OFDM18	= 0x7,
301 	RTW89_HW_RATE_OFDM24	= 0x8,
302 	RTW89_HW_RATE_OFDM36	= 0x9,
303 	RTW89_HW_RATE_OFDM48	= 0xA,
304 	RTW89_HW_RATE_OFDM54	= 0xB,
305 	RTW89_HW_RATE_MCS0	= 0x80,
306 	RTW89_HW_RATE_MCS1	= 0x81,
307 	RTW89_HW_RATE_MCS2	= 0x82,
308 	RTW89_HW_RATE_MCS3	= 0x83,
309 	RTW89_HW_RATE_MCS4	= 0x84,
310 	RTW89_HW_RATE_MCS5	= 0x85,
311 	RTW89_HW_RATE_MCS6	= 0x86,
312 	RTW89_HW_RATE_MCS7	= 0x87,
313 	RTW89_HW_RATE_MCS8	= 0x88,
314 	RTW89_HW_RATE_MCS9	= 0x89,
315 	RTW89_HW_RATE_MCS10	= 0x8A,
316 	RTW89_HW_RATE_MCS11	= 0x8B,
317 	RTW89_HW_RATE_MCS12	= 0x8C,
318 	RTW89_HW_RATE_MCS13	= 0x8D,
319 	RTW89_HW_RATE_MCS14	= 0x8E,
320 	RTW89_HW_RATE_MCS15	= 0x8F,
321 	RTW89_HW_RATE_MCS16	= 0x90,
322 	RTW89_HW_RATE_MCS17	= 0x91,
323 	RTW89_HW_RATE_MCS18	= 0x92,
324 	RTW89_HW_RATE_MCS19	= 0x93,
325 	RTW89_HW_RATE_MCS20	= 0x94,
326 	RTW89_HW_RATE_MCS21	= 0x95,
327 	RTW89_HW_RATE_MCS22	= 0x96,
328 	RTW89_HW_RATE_MCS23	= 0x97,
329 	RTW89_HW_RATE_MCS24	= 0x98,
330 	RTW89_HW_RATE_MCS25	= 0x99,
331 	RTW89_HW_RATE_MCS26	= 0x9A,
332 	RTW89_HW_RATE_MCS27	= 0x9B,
333 	RTW89_HW_RATE_MCS28	= 0x9C,
334 	RTW89_HW_RATE_MCS29	= 0x9D,
335 	RTW89_HW_RATE_MCS30	= 0x9E,
336 	RTW89_HW_RATE_MCS31	= 0x9F,
337 	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
338 	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
339 	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
340 	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
341 	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
342 	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
343 	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
344 	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
345 	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
346 	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
347 	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
348 	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
349 	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
350 	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
351 	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
352 	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
353 	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
354 	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
355 	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
356 	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
357 	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
358 	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
359 	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
360 	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
361 	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
362 	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
363 	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
364 	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
365 	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
366 	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
367 	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
368 	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
369 	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
370 	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
371 	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
372 	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
373 	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
374 	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
375 	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
376 	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
377 	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
378 	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
379 	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
380 	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
381 	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
382 	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
383 	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
384 	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
385 	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
386 	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
387 	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
388 	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
389 	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
390 	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
391 	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
392 	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
393 	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
394 	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
395 	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
396 	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
397 	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
398 	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
399 	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
400 	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
401 	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
402 	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
403 	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
404 	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
405 	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
406 	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
407 	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
408 	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
409 	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
410 	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
411 	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
412 	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
413 	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
414 	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
415 	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
416 	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
417 	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
418 	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
419 	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
420 	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
421 	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
422 	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
423 	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
424 	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
425 
426 	RTW89_HW_RATE_V1_MCS0		= 0x100,
427 	RTW89_HW_RATE_V1_MCS1		= 0x101,
428 	RTW89_HW_RATE_V1_MCS2		= 0x102,
429 	RTW89_HW_RATE_V1_MCS3		= 0x103,
430 	RTW89_HW_RATE_V1_MCS4		= 0x104,
431 	RTW89_HW_RATE_V1_MCS5		= 0x105,
432 	RTW89_HW_RATE_V1_MCS6		= 0x106,
433 	RTW89_HW_RATE_V1_MCS7		= 0x107,
434 	RTW89_HW_RATE_V1_MCS8		= 0x108,
435 	RTW89_HW_RATE_V1_MCS9		= 0x109,
436 	RTW89_HW_RATE_V1_MCS10		= 0x10A,
437 	RTW89_HW_RATE_V1_MCS11		= 0x10B,
438 	RTW89_HW_RATE_V1_MCS12		= 0x10C,
439 	RTW89_HW_RATE_V1_MCS13		= 0x10D,
440 	RTW89_HW_RATE_V1_MCS14		= 0x10E,
441 	RTW89_HW_RATE_V1_MCS15		= 0x10F,
442 	RTW89_HW_RATE_V1_MCS16		= 0x110,
443 	RTW89_HW_RATE_V1_MCS17		= 0x111,
444 	RTW89_HW_RATE_V1_MCS18		= 0x112,
445 	RTW89_HW_RATE_V1_MCS19		= 0x113,
446 	RTW89_HW_RATE_V1_MCS20		= 0x114,
447 	RTW89_HW_RATE_V1_MCS21		= 0x115,
448 	RTW89_HW_RATE_V1_MCS22		= 0x116,
449 	RTW89_HW_RATE_V1_MCS23		= 0x117,
450 	RTW89_HW_RATE_V1_MCS24		= 0x118,
451 	RTW89_HW_RATE_V1_MCS25		= 0x119,
452 	RTW89_HW_RATE_V1_MCS26		= 0x11A,
453 	RTW89_HW_RATE_V1_MCS27		= 0x11B,
454 	RTW89_HW_RATE_V1_MCS28		= 0x11C,
455 	RTW89_HW_RATE_V1_MCS29		= 0x11D,
456 	RTW89_HW_RATE_V1_MCS30		= 0x11E,
457 	RTW89_HW_RATE_V1_MCS31		= 0x11F,
458 	RTW89_HW_RATE_V1_VHT_NSS1_MCS0	= 0x200,
459 	RTW89_HW_RATE_V1_VHT_NSS1_MCS1	= 0x201,
460 	RTW89_HW_RATE_V1_VHT_NSS1_MCS2	= 0x202,
461 	RTW89_HW_RATE_V1_VHT_NSS1_MCS3	= 0x203,
462 	RTW89_HW_RATE_V1_VHT_NSS1_MCS4	= 0x204,
463 	RTW89_HW_RATE_V1_VHT_NSS1_MCS5	= 0x205,
464 	RTW89_HW_RATE_V1_VHT_NSS1_MCS6	= 0x206,
465 	RTW89_HW_RATE_V1_VHT_NSS1_MCS7	= 0x207,
466 	RTW89_HW_RATE_V1_VHT_NSS1_MCS8	= 0x208,
467 	RTW89_HW_RATE_V1_VHT_NSS1_MCS9	= 0x209,
468 	RTW89_HW_RATE_V1_VHT_NSS1_MCS10	= 0x20A,
469 	RTW89_HW_RATE_V1_VHT_NSS1_MCS11	= 0x20B,
470 	RTW89_HW_RATE_V1_VHT_NSS2_MCS0	= 0x220,
471 	RTW89_HW_RATE_V1_VHT_NSS2_MCS1	= 0x221,
472 	RTW89_HW_RATE_V1_VHT_NSS2_MCS2	= 0x222,
473 	RTW89_HW_RATE_V1_VHT_NSS2_MCS3	= 0x223,
474 	RTW89_HW_RATE_V1_VHT_NSS2_MCS4	= 0x224,
475 	RTW89_HW_RATE_V1_VHT_NSS2_MCS5	= 0x225,
476 	RTW89_HW_RATE_V1_VHT_NSS2_MCS6	= 0x226,
477 	RTW89_HW_RATE_V1_VHT_NSS2_MCS7	= 0x227,
478 	RTW89_HW_RATE_V1_VHT_NSS2_MCS8	= 0x228,
479 	RTW89_HW_RATE_V1_VHT_NSS2_MCS9	= 0x229,
480 	RTW89_HW_RATE_V1_VHT_NSS2_MCS10	= 0x22A,
481 	RTW89_HW_RATE_V1_VHT_NSS2_MCS11	= 0x22B,
482 	RTW89_HW_RATE_V1_VHT_NSS3_MCS0	= 0x240,
483 	RTW89_HW_RATE_V1_VHT_NSS3_MCS1	= 0x241,
484 	RTW89_HW_RATE_V1_VHT_NSS3_MCS2	= 0x242,
485 	RTW89_HW_RATE_V1_VHT_NSS3_MCS3	= 0x243,
486 	RTW89_HW_RATE_V1_VHT_NSS3_MCS4	= 0x244,
487 	RTW89_HW_RATE_V1_VHT_NSS3_MCS5	= 0x245,
488 	RTW89_HW_RATE_V1_VHT_NSS3_MCS6	= 0x246,
489 	RTW89_HW_RATE_V1_VHT_NSS3_MCS7	= 0x247,
490 	RTW89_HW_RATE_V1_VHT_NSS3_MCS8	= 0x248,
491 	RTW89_HW_RATE_V1_VHT_NSS3_MCS9	= 0x249,
492 	RTW89_HW_RATE_V1_VHT_NSS3_MCS10	= 0x24A,
493 	RTW89_HW_RATE_V1_VHT_NSS3_MCS11	= 0x24B,
494 	RTW89_HW_RATE_V1_VHT_NSS4_MCS0	= 0x260,
495 	RTW89_HW_RATE_V1_VHT_NSS4_MCS1	= 0x261,
496 	RTW89_HW_RATE_V1_VHT_NSS4_MCS2	= 0x262,
497 	RTW89_HW_RATE_V1_VHT_NSS4_MCS3	= 0x263,
498 	RTW89_HW_RATE_V1_VHT_NSS4_MCS4	= 0x264,
499 	RTW89_HW_RATE_V1_VHT_NSS4_MCS5	= 0x265,
500 	RTW89_HW_RATE_V1_VHT_NSS4_MCS6	= 0x266,
501 	RTW89_HW_RATE_V1_VHT_NSS4_MCS7	= 0x267,
502 	RTW89_HW_RATE_V1_VHT_NSS4_MCS8	= 0x268,
503 	RTW89_HW_RATE_V1_VHT_NSS4_MCS9	= 0x269,
504 	RTW89_HW_RATE_V1_VHT_NSS4_MCS10	= 0x26A,
505 	RTW89_HW_RATE_V1_VHT_NSS4_MCS11	= 0x26B,
506 	RTW89_HW_RATE_V1_HE_NSS1_MCS0	= 0x300,
507 	RTW89_HW_RATE_V1_HE_NSS1_MCS1	= 0x301,
508 	RTW89_HW_RATE_V1_HE_NSS1_MCS2	= 0x302,
509 	RTW89_HW_RATE_V1_HE_NSS1_MCS3	= 0x303,
510 	RTW89_HW_RATE_V1_HE_NSS1_MCS4	= 0x304,
511 	RTW89_HW_RATE_V1_HE_NSS1_MCS5	= 0x305,
512 	RTW89_HW_RATE_V1_HE_NSS1_MCS6	= 0x306,
513 	RTW89_HW_RATE_V1_HE_NSS1_MCS7	= 0x307,
514 	RTW89_HW_RATE_V1_HE_NSS1_MCS8	= 0x308,
515 	RTW89_HW_RATE_V1_HE_NSS1_MCS9	= 0x309,
516 	RTW89_HW_RATE_V1_HE_NSS1_MCS10	= 0x30A,
517 	RTW89_HW_RATE_V1_HE_NSS1_MCS11	= 0x30B,
518 	RTW89_HW_RATE_V1_HE_NSS2_MCS0	= 0x320,
519 	RTW89_HW_RATE_V1_HE_NSS2_MCS1	= 0x321,
520 	RTW89_HW_RATE_V1_HE_NSS2_MCS2	= 0x322,
521 	RTW89_HW_RATE_V1_HE_NSS2_MCS3	= 0x323,
522 	RTW89_HW_RATE_V1_HE_NSS2_MCS4	= 0x324,
523 	RTW89_HW_RATE_V1_HE_NSS2_MCS5	= 0x325,
524 	RTW89_HW_RATE_V1_HE_NSS2_MCS6	= 0x326,
525 	RTW89_HW_RATE_V1_HE_NSS2_MCS7	= 0x327,
526 	RTW89_HW_RATE_V1_HE_NSS2_MCS8	= 0x328,
527 	RTW89_HW_RATE_V1_HE_NSS2_MCS9	= 0x329,
528 	RTW89_HW_RATE_V1_HE_NSS2_MCS10	= 0x32A,
529 	RTW89_HW_RATE_V1_HE_NSS2_MCS11	= 0x32B,
530 	RTW89_HW_RATE_V1_HE_NSS3_MCS0	= 0x340,
531 	RTW89_HW_RATE_V1_HE_NSS3_MCS1	= 0x341,
532 	RTW89_HW_RATE_V1_HE_NSS3_MCS2	= 0x342,
533 	RTW89_HW_RATE_V1_HE_NSS3_MCS3	= 0x343,
534 	RTW89_HW_RATE_V1_HE_NSS3_MCS4	= 0x344,
535 	RTW89_HW_RATE_V1_HE_NSS3_MCS5	= 0x345,
536 	RTW89_HW_RATE_V1_HE_NSS3_MCS6	= 0x346,
537 	RTW89_HW_RATE_V1_HE_NSS3_MCS7	= 0x347,
538 	RTW89_HW_RATE_V1_HE_NSS3_MCS8	= 0x348,
539 	RTW89_HW_RATE_V1_HE_NSS3_MCS9	= 0x349,
540 	RTW89_HW_RATE_V1_HE_NSS3_MCS10	= 0x34A,
541 	RTW89_HW_RATE_V1_HE_NSS3_MCS11	= 0x34B,
542 	RTW89_HW_RATE_V1_HE_NSS4_MCS0	= 0x360,
543 	RTW89_HW_RATE_V1_HE_NSS4_MCS1	= 0x361,
544 	RTW89_HW_RATE_V1_HE_NSS4_MCS2	= 0x362,
545 	RTW89_HW_RATE_V1_HE_NSS4_MCS3	= 0x363,
546 	RTW89_HW_RATE_V1_HE_NSS4_MCS4	= 0x364,
547 	RTW89_HW_RATE_V1_HE_NSS4_MCS5	= 0x365,
548 	RTW89_HW_RATE_V1_HE_NSS4_MCS6	= 0x366,
549 	RTW89_HW_RATE_V1_HE_NSS4_MCS7	= 0x367,
550 	RTW89_HW_RATE_V1_HE_NSS4_MCS8	= 0x368,
551 	RTW89_HW_RATE_V1_HE_NSS4_MCS9	= 0x369,
552 	RTW89_HW_RATE_V1_HE_NSS4_MCS10	= 0x36A,
553 	RTW89_HW_RATE_V1_HE_NSS4_MCS11	= 0x36B,
554 	RTW89_HW_RATE_V1_EHT_NSS1_MCS0	= 0x400,
555 	RTW89_HW_RATE_V1_EHT_NSS1_MCS1	= 0x401,
556 	RTW89_HW_RATE_V1_EHT_NSS1_MCS2	= 0x402,
557 	RTW89_HW_RATE_V1_EHT_NSS1_MCS3	= 0x403,
558 	RTW89_HW_RATE_V1_EHT_NSS1_MCS4	= 0x404,
559 	RTW89_HW_RATE_V1_EHT_NSS1_MCS5	= 0x405,
560 	RTW89_HW_RATE_V1_EHT_NSS1_MCS6	= 0x406,
561 	RTW89_HW_RATE_V1_EHT_NSS1_MCS7	= 0x407,
562 	RTW89_HW_RATE_V1_EHT_NSS1_MCS8	= 0x408,
563 	RTW89_HW_RATE_V1_EHT_NSS1_MCS9	= 0x409,
564 	RTW89_HW_RATE_V1_EHT_NSS1_MCS10	= 0x40A,
565 	RTW89_HW_RATE_V1_EHT_NSS1_MCS11	= 0x40B,
566 	RTW89_HW_RATE_V1_EHT_NSS1_MCS12	= 0x40C,
567 	RTW89_HW_RATE_V1_EHT_NSS1_MCS13	= 0x40D,
568 	RTW89_HW_RATE_V1_EHT_NSS1_MCS14	= 0x40E,
569 	RTW89_HW_RATE_V1_EHT_NSS1_MCS15	= 0x40F,
570 	RTW89_HW_RATE_V1_EHT_NSS2_MCS0	= 0x420,
571 	RTW89_HW_RATE_V1_EHT_NSS2_MCS1	= 0x421,
572 	RTW89_HW_RATE_V1_EHT_NSS2_MCS2	= 0x422,
573 	RTW89_HW_RATE_V1_EHT_NSS2_MCS3	= 0x423,
574 	RTW89_HW_RATE_V1_EHT_NSS2_MCS4	= 0x424,
575 	RTW89_HW_RATE_V1_EHT_NSS2_MCS5	= 0x425,
576 	RTW89_HW_RATE_V1_EHT_NSS2_MCS6	= 0x426,
577 	RTW89_HW_RATE_V1_EHT_NSS2_MCS7	= 0x427,
578 	RTW89_HW_RATE_V1_EHT_NSS2_MCS8	= 0x428,
579 	RTW89_HW_RATE_V1_EHT_NSS2_MCS9	= 0x429,
580 	RTW89_HW_RATE_V1_EHT_NSS2_MCS10	= 0x42A,
581 	RTW89_HW_RATE_V1_EHT_NSS2_MCS11	= 0x42B,
582 	RTW89_HW_RATE_V1_EHT_NSS2_MCS12	= 0x42C,
583 	RTW89_HW_RATE_V1_EHT_NSS2_MCS13	= 0x42D,
584 	RTW89_HW_RATE_V1_EHT_NSS3_MCS0	= 0x440,
585 	RTW89_HW_RATE_V1_EHT_NSS3_MCS1	= 0x441,
586 	RTW89_HW_RATE_V1_EHT_NSS3_MCS2	= 0x442,
587 	RTW89_HW_RATE_V1_EHT_NSS3_MCS3	= 0x443,
588 	RTW89_HW_RATE_V1_EHT_NSS3_MCS4	= 0x444,
589 	RTW89_HW_RATE_V1_EHT_NSS3_MCS5	= 0x445,
590 	RTW89_HW_RATE_V1_EHT_NSS3_MCS6	= 0x446,
591 	RTW89_HW_RATE_V1_EHT_NSS3_MCS7	= 0x447,
592 	RTW89_HW_RATE_V1_EHT_NSS3_MCS8	= 0x448,
593 	RTW89_HW_RATE_V1_EHT_NSS3_MCS9	= 0x449,
594 	RTW89_HW_RATE_V1_EHT_NSS3_MCS10	= 0x44A,
595 	RTW89_HW_RATE_V1_EHT_NSS3_MCS11	= 0x44B,
596 	RTW89_HW_RATE_V1_EHT_NSS3_MCS12	= 0x44C,
597 	RTW89_HW_RATE_V1_EHT_NSS3_MCS13	= 0x44D,
598 	RTW89_HW_RATE_V1_EHT_NSS4_MCS0	= 0x460,
599 	RTW89_HW_RATE_V1_EHT_NSS4_MCS1	= 0x461,
600 	RTW89_HW_RATE_V1_EHT_NSS4_MCS2	= 0x462,
601 	RTW89_HW_RATE_V1_EHT_NSS4_MCS3	= 0x463,
602 	RTW89_HW_RATE_V1_EHT_NSS4_MCS4	= 0x464,
603 	RTW89_HW_RATE_V1_EHT_NSS4_MCS5	= 0x465,
604 	RTW89_HW_RATE_V1_EHT_NSS4_MCS6	= 0x466,
605 	RTW89_HW_RATE_V1_EHT_NSS4_MCS7	= 0x467,
606 	RTW89_HW_RATE_V1_EHT_NSS4_MCS8	= 0x468,
607 	RTW89_HW_RATE_V1_EHT_NSS4_MCS9	= 0x469,
608 	RTW89_HW_RATE_V1_EHT_NSS4_MCS10	= 0x46A,
609 	RTW89_HW_RATE_V1_EHT_NSS4_MCS11	= 0x46B,
610 	RTW89_HW_RATE_V1_EHT_NSS4_MCS12	= 0x46C,
611 	RTW89_HW_RATE_V1_EHT_NSS4_MCS13	= 0x46D,
612 
613 	RTW89_HW_RATE_NR,
614 	RTW89_HW_RATE_INVAL,
615 
616 	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
617 	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
618 	RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
619 	RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
620 };
621 
622 /* 2G channels,
623  * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
624  */
625 #define RTW89_2G_CH_NUM 14
626 
627 /* 5G channels,
628  * 36, 38, 40, 42, 44, 46, 48, 50,
629  * 52, 54, 56, 58, 60, 62, 64,
630  * 100, 102, 104, 106, 108, 110, 112, 114,
631  * 116, 118, 120, 122, 124, 126, 128, 130,
632  * 132, 134, 136, 138, 140, 142, 144,
633  * 149, 151, 153, 155, 157, 159, 161, 163,
634  * 165, 167, 169, 171, 173, 175, 177
635  */
636 #define RTW89_5G_CH_NUM 53
637 
638 /* 6G channels,
639  * 1, 3, 5, 7, 9, 11, 13, 15,
640  * 17, 19, 21, 23, 25, 27, 29, 33,
641  * 35, 37, 39, 41, 43, 45, 47, 49,
642  * 51, 53, 55, 57, 59, 61, 65, 67,
643  * 69, 71, 73, 75, 77, 79, 81, 83,
644  * 85, 87, 89, 91, 93, 97, 99, 101,
645  * 103, 105, 107, 109, 111, 113, 115, 117,
646  * 119, 121, 123, 125, 129, 131, 133, 135,
647  * 137, 139, 141, 143, 145, 147, 149, 151,
648  * 153, 155, 157, 161, 163, 165, 167, 169,
649  * 171, 173, 175, 177, 179, 181, 183, 185,
650  * 187, 189, 193, 195, 197, 199, 201, 203,
651  * 205, 207, 209, 211, 213, 215, 217, 219,
652  * 221, 225, 227, 229, 231, 233, 235, 237,
653  * 239, 241, 243, 245, 247, 249, 251, 253,
654  */
655 #define RTW89_6G_CH_NUM 120
656 
657 enum rtw89_rate_section {
658 	RTW89_RS_CCK,
659 	RTW89_RS_OFDM,
660 	RTW89_RS_MCS, /* for HT/VHT/HE */
661 	RTW89_RS_HEDCM,
662 	RTW89_RS_OFFSET,
663 	RTW89_RS_NUM,
664 	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
665 	RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
666 };
667 
668 enum rtw89_rate_offset_indexes {
669 	RTW89_RATE_OFFSET_HE,
670 	RTW89_RATE_OFFSET_VHT,
671 	RTW89_RATE_OFFSET_HT,
672 	RTW89_RATE_OFFSET_OFDM,
673 	RTW89_RATE_OFFSET_CCK,
674 	RTW89_RATE_OFFSET_DLRU_EHT,
675 	RTW89_RATE_OFFSET_DLRU_HE,
676 	RTW89_RATE_OFFSET_EHT,
677 	__RTW89_RATE_OFFSET_NUM,
678 
679 	RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
680 	RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
681 };
682 
683 enum rtw89_rate_num {
684 	RTW89_RATE_CCK_NUM	= 4,
685 	RTW89_RATE_OFDM_NUM	= 8,
686 	RTW89_RATE_HEDCM_NUM	= 4, /* for HEDCM MCS0/1/3/4 */
687 
688 	RTW89_RATE_MCS_NUM_AX	= 12,
689 	RTW89_RATE_MCS_NUM_BE	= 16,
690 	__RTW89_RATE_MCS_NUM	= 16,
691 };
692 
693 enum rtw89_nss {
694 	RTW89_NSS_1		= 0,
695 	RTW89_NSS_2		= 1,
696 	/* HE DCM only support 1ss and 2ss */
697 	RTW89_NSS_HEDCM_NUM	= RTW89_NSS_2 + 1,
698 	RTW89_NSS_3		= 2,
699 	RTW89_NSS_4		= 3,
700 	RTW89_NSS_NUM,
701 };
702 
703 enum rtw89_ntx {
704 	RTW89_1TX	= 0,
705 	RTW89_2TX	= 1,
706 	RTW89_NTX_NUM,
707 };
708 
709 enum rtw89_beamforming_type {
710 	RTW89_NONBF	= 0,
711 	RTW89_BF	= 1,
712 	RTW89_BF_NUM,
713 };
714 
715 enum rtw89_ofdma_type {
716 	RTW89_NON_OFDMA	= 0,
717 	RTW89_OFDMA	= 1,
718 	RTW89_OFDMA_NUM,
719 };
720 
721 enum rtw89_regulation_type {
722 	RTW89_WW	= 0,
723 	RTW89_ETSI	= 1,
724 	RTW89_FCC	= 2,
725 	RTW89_MKK	= 3,
726 	RTW89_NA	= 4,
727 	RTW89_IC	= 5,
728 	RTW89_KCC	= 6,
729 	RTW89_ACMA	= 7,
730 	RTW89_NCC	= 8,
731 	RTW89_MEXICO	= 9,
732 	RTW89_CHILE	= 10,
733 	RTW89_UKRAINE	= 11,
734 	RTW89_CN	= 12,
735 	RTW89_QATAR	= 13,
736 	RTW89_UK	= 14,
737 	RTW89_THAILAND	= 15,
738 	RTW89_REGD_NUM,
739 };
740 
741 enum rtw89_reg_6ghz_power {
742 	RTW89_REG_6GHZ_POWER_VLP = 0,
743 	RTW89_REG_6GHZ_POWER_LPI = 1,
744 	RTW89_REG_6GHZ_POWER_STD = 2,
745 
746 	NUM_OF_RTW89_REG_6GHZ_POWER,
747 	RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
748 };
749 
750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
751 
752 /* calculate based on ieee80211 Transmit Power Envelope */
753 struct rtw89_reg_6ghz_tpe {
754 	bool valid;
755 	s8 constraint; /* unit: dBm */
756 };
757 
758 enum rtw89_fw_pkt_ofld_type {
759 	RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
760 	RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
761 	RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
762 	RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
763 	RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
764 	RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
765 	RTW89_PKT_OFLD_TYPE_NDP = 6,
766 	RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
767 	RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
768 	RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
769 	RTW89_PKT_OFLD_TYPE_NUM,
770 };
771 
772 struct rtw89_txpwr_byrate {
773 	s8 cck[RTW89_RATE_CCK_NUM];
774 	s8 ofdm[RTW89_RATE_OFDM_NUM];
775 	s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
776 	s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
777 	s8 offset[__RTW89_RATE_OFFSET_NUM];
778 	s8 trap;
779 };
780 
781 struct rtw89_rate_desc {
782 	enum rtw89_nss nss;
783 	enum rtw89_rate_section rs;
784 	enum rtw89_ofdma_type ofdma;
785 	u8 idx;
786 };
787 
788 #define PHY_STS_HDR_LEN 8
789 #define RF_PATH_MAX 4
790 #define RTW89_MAX_PPDU_CNT 8
791 struct rtw89_rx_phy_ppdu {
792 	void *buf;
793 	u32 len;
794 	u8 rssi_avg;
795 	u8 rssi[RF_PATH_MAX];
796 	u8 mac_id;
797 	u8 chan_idx;
798 	u8 ie;
799 	u16 rate;
800 	u8 rpl_avg;
801 	u8 rpl_path[RF_PATH_MAX];
802 	u8 rpl_fd[RF_PATH_MAX];
803 	u8 bw_idx;
804 	u8 rx_path_en;
805 	struct {
806 		bool has;
807 		u8 avg_snr;
808 		u8 evm_max;
809 		u8 evm_min;
810 	} ofdm;
811 	bool has_data;
812 	bool has_bcn;
813 	bool ldpc;
814 	bool stbc;
815 	bool to_self;
816 	bool valid;
817 	bool hdr_2_en;
818 };
819 
820 enum rtw89_mac_idx {
821 	RTW89_MAC_0 = 0,
822 	RTW89_MAC_1 = 1,
823 	RTW89_MAC_NUM,
824 };
825 
826 enum rtw89_phy_idx {
827 	RTW89_PHY_0 = 0,
828 	RTW89_PHY_1 = 1,
829 	RTW89_PHY_MAX
830 };
831 
832 enum rtw89_chanctx_idx {
833 	RTW89_CHANCTX_0 = 0,
834 	RTW89_CHANCTX_1 = 1,
835 
836 	NUM_OF_RTW89_CHANCTX,
837 	RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
838 };
839 
840 enum rtw89_rf_path {
841 	RF_PATH_A = 0,
842 	RF_PATH_B = 1,
843 	RF_PATH_C = 2,
844 	RF_PATH_D = 3,
845 	RF_PATH_AB,
846 	RF_PATH_AC,
847 	RF_PATH_AD,
848 	RF_PATH_BC,
849 	RF_PATH_BD,
850 	RF_PATH_CD,
851 	RF_PATH_ABC,
852 	RF_PATH_ABD,
853 	RF_PATH_ACD,
854 	RF_PATH_BCD,
855 	RF_PATH_ABCD,
856 };
857 
858 enum rtw89_rf_path_bit {
859 	RF_A	= BIT(0),
860 	RF_B	= BIT(1),
861 	RF_C	= BIT(2),
862 	RF_D	= BIT(3),
863 
864 	RF_AB	= (RF_A | RF_B),
865 	RF_AC	= (RF_A | RF_C),
866 	RF_AD	= (RF_A | RF_D),
867 	RF_BC	= (RF_B | RF_C),
868 	RF_BD	= (RF_B | RF_D),
869 	RF_CD	= (RF_C | RF_D),
870 
871 	RF_ABC	= (RF_A | RF_B | RF_C),
872 	RF_ABD	= (RF_A | RF_B | RF_D),
873 	RF_ACD	= (RF_A | RF_C | RF_D),
874 	RF_BCD	= (RF_B | RF_C | RF_D),
875 
876 	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
877 };
878 
879 enum rtw89_bandwidth {
880 	RTW89_CHANNEL_WIDTH_20	= 0,
881 	RTW89_CHANNEL_WIDTH_40	= 1,
882 	RTW89_CHANNEL_WIDTH_80	= 2,
883 	RTW89_CHANNEL_WIDTH_160	= 3,
884 	RTW89_CHANNEL_WIDTH_320	= 4,
885 
886 	/* keep index order above */
887 	RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
888 
889 	RTW89_CHANNEL_WIDTH_80_80 = 5,
890 	RTW89_CHANNEL_WIDTH_5 = 6,
891 	RTW89_CHANNEL_WIDTH_10 = 7,
892 };
893 
894 enum rtw89_ps_mode {
895 	RTW89_PS_MODE_NONE	= 0,
896 	RTW89_PS_MODE_RFOFF	= 1,
897 	RTW89_PS_MODE_CLK_GATED	= 2,
898 	RTW89_PS_MODE_PWR_GATED	= 3,
899 };
900 
901 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
902 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
903 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
904 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
905 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
906 
907 enum rtw89_pe_duration {
908 	RTW89_PE_DURATION_0 = 0,
909 	RTW89_PE_DURATION_8 = 1,
910 	RTW89_PE_DURATION_16 = 2,
911 	RTW89_PE_DURATION_16_20 = 3,
912 };
913 
914 enum rtw89_ru_bandwidth {
915 	RTW89_RU26 = 0,
916 	RTW89_RU52 = 1,
917 	RTW89_RU106 = 2,
918 	RTW89_RU52_26 = 3,
919 	RTW89_RU106_26 = 4,
920 	RTW89_RU_NUM,
921 };
922 
923 enum rtw89_sc_offset {
924 	RTW89_SC_DONT_CARE	= 0,
925 	RTW89_SC_20_UPPER	= 1,
926 	RTW89_SC_20_LOWER	= 2,
927 	RTW89_SC_20_UPMOST	= 3,
928 	RTW89_SC_20_LOWEST	= 4,
929 	RTW89_SC_20_UP2X	= 5,
930 	RTW89_SC_20_LOW2X	= 6,
931 	RTW89_SC_20_UP3X	= 7,
932 	RTW89_SC_20_LOW3X	= 8,
933 	RTW89_SC_40_UPPER	= 9,
934 	RTW89_SC_40_LOWER	= 10,
935 };
936 
937 /* only mgd features can be added to the enum */
938 enum rtw89_wow_flags {
939 	RTW89_WOW_FLAG_EN_MAGIC_PKT,
940 	RTW89_WOW_FLAG_EN_REKEY_PKT,
941 	RTW89_WOW_FLAG_EN_DISCONNECT,
942 	RTW89_WOW_FLAG_EN_PATTERN,
943 	RTW89_WOW_FLAG_NUM,
944 };
945 
946 struct rtw89_chan {
947 	u8 channel;
948 	u8 primary_channel;
949 	enum rtw89_band band_type;
950 	enum rtw89_bandwidth band_width;
951 
952 	/* The follow-up are derived from the above. We must ensure that it
953 	 * is assigned correctly in rtw89_chan_create() if new one is added.
954 	 */
955 	u32 freq;
956 	enum rtw89_subband subband_type;
957 	enum rtw89_sc_offset pri_ch_idx;
958 	u8 pri_sb_idx;
959 };
960 
961 struct rtw89_chan_rcd {
962 	u8 prev_primary_channel;
963 	enum rtw89_band prev_band_type;
964 	bool band_changed;
965 };
966 
967 struct rtw89_channel_help_params {
968 	u32 tx_en;
969 };
970 
971 struct rtw89_port_reg {
972 	u32 port_cfg;
973 	u32 tbtt_prohib;
974 	u32 bcn_area;
975 	u32 bcn_early;
976 	u32 tbtt_early;
977 	u32 tbtt_agg;
978 	u32 bcn_space;
979 	u32 bcn_forcetx;
980 	u32 bcn_err_cnt;
981 	u32 bcn_err_flag;
982 	u32 dtim_ctrl;
983 	u32 tbtt_shift;
984 	u32 bcn_cnt_tmr;
985 	u32 tsftr_l;
986 	u32 tsftr_h;
987 	u32 md_tsft;
988 	u32 bss_color;
989 	u32 mbssid;
990 	u32 mbssid_drop;
991 	u32 tsf_sync;
992 	u32 ptcl_dbg;
993 	u32 ptcl_dbg_info;
994 	u32 bcn_drop_all;
995 	u32 hiq_win[RTW89_PORT_NUM];
996 };
997 
998 struct rtw89_txwd_body {
999 	__le32 dword0;
1000 	__le32 dword1;
1001 	__le32 dword2;
1002 	__le32 dword3;
1003 	__le32 dword4;
1004 	__le32 dword5;
1005 } __packed;
1006 
1007 struct rtw89_txwd_body_v1 {
1008 	__le32 dword0;
1009 	__le32 dword1;
1010 	__le32 dword2;
1011 	__le32 dword3;
1012 	__le32 dword4;
1013 	__le32 dword5;
1014 	__le32 dword6;
1015 	__le32 dword7;
1016 } __packed;
1017 
1018 struct rtw89_txwd_body_v2 {
1019 	__le32 dword0;
1020 	__le32 dword1;
1021 	__le32 dword2;
1022 	__le32 dword3;
1023 	__le32 dword4;
1024 	__le32 dword5;
1025 	__le32 dword6;
1026 	__le32 dword7;
1027 } __packed;
1028 
1029 struct rtw89_txwd_info {
1030 	__le32 dword0;
1031 	__le32 dword1;
1032 	__le32 dword2;
1033 	__le32 dword3;
1034 	__le32 dword4;
1035 	__le32 dword5;
1036 } __packed;
1037 
1038 struct rtw89_txwd_info_v2 {
1039 	__le32 dword0;
1040 	__le32 dword1;
1041 	__le32 dword2;
1042 	__le32 dword3;
1043 	__le32 dword4;
1044 	__le32 dword5;
1045 	__le32 dword6;
1046 	__le32 dword7;
1047 } __packed;
1048 
1049 struct rtw89_rx_desc_info {
1050 	u16 pkt_size;
1051 	u8 pkt_type;
1052 	u8 drv_info_size;
1053 	u8 phy_rpt_size;
1054 	u8 hdr_cnv_size;
1055 	u8 shift;
1056 	u8 wl_hd_iv_len;
1057 	bool long_rxdesc;
1058 	bool bb_sel;
1059 	bool mac_info_valid;
1060 	u16 data_rate;
1061 	u8 gi_ltf;
1062 	u8 bw;
1063 	u32 free_run_cnt;
1064 	u8 user_id;
1065 	bool sr_en;
1066 	u8 ppdu_cnt;
1067 	u8 ppdu_type;
1068 	bool icv_err;
1069 	bool crc32_err;
1070 	bool hw_dec;
1071 	bool sw_dec;
1072 	bool addr1_match;
1073 	u8 frag;
1074 	u16 seq;
1075 	u8 frame_type;
1076 	u8 rx_pl_id;
1077 	bool addr_cam_valid;
1078 	u8 addr_cam_id;
1079 	u8 sec_cam_id;
1080 	u8 mac_id;
1081 	u16 offset;
1082 	u16 rxd_len;
1083 	bool ready;
1084 };
1085 
1086 struct rtw89_rxdesc_short {
1087 	__le32 dword0;
1088 	__le32 dword1;
1089 	__le32 dword2;
1090 	__le32 dword3;
1091 } __packed;
1092 
1093 struct rtw89_rxdesc_short_v2 {
1094 	__le32 dword0;
1095 	__le32 dword1;
1096 	__le32 dword2;
1097 	__le32 dword3;
1098 	__le32 dword4;
1099 	__le32 dword5;
1100 } __packed;
1101 
1102 struct rtw89_rxdesc_long {
1103 	__le32 dword0;
1104 	__le32 dword1;
1105 	__le32 dword2;
1106 	__le32 dword3;
1107 	__le32 dword4;
1108 	__le32 dword5;
1109 	__le32 dword6;
1110 	__le32 dword7;
1111 } __packed;
1112 
1113 struct rtw89_rxdesc_long_v2 {
1114 	__le32 dword0;
1115 	__le32 dword1;
1116 	__le32 dword2;
1117 	__le32 dword3;
1118 	__le32 dword4;
1119 	__le32 dword5;
1120 	__le32 dword6;
1121 	__le32 dword7;
1122 	__le32 dword8;
1123 	__le32 dword9;
1124 } __packed;
1125 
1126 struct rtw89_tx_desc_info {
1127 	u16 pkt_size;
1128 	u8 wp_offset;
1129 	u8 mac_id;
1130 	u8 qsel;
1131 	u8 ch_dma;
1132 	u8 hdr_llc_len;
1133 	bool is_bmc;
1134 	bool en_wd_info;
1135 	bool wd_page;
1136 	bool use_rate;
1137 	bool dis_data_fb;
1138 	bool tid_indicate;
1139 	bool agg_en;
1140 	bool bk;
1141 	u8 ampdu_density;
1142 	u8 ampdu_num;
1143 	bool sec_en;
1144 	u8 addr_info_nr;
1145 	u8 sec_keyid;
1146 	u8 sec_type;
1147 	u8 sec_cam_idx;
1148 	u8 sec_seq[6];
1149 	u16 data_rate;
1150 	u16 data_retry_lowest_rate;
1151 	bool fw_dl;
1152 	u16 seq;
1153 	bool a_ctrl_bsr;
1154 	u8 hw_ssn_sel;
1155 #define RTW89_MGMT_HW_SSN_SEL	1
1156 	u8 hw_seq_mode;
1157 #define RTW89_MGMT_HW_SEQ_MODE	1
1158 	bool hiq;
1159 	u8 port;
1160 	bool er_cap;
1161 	bool stbc;
1162 	bool ldpc;
1163 };
1164 
1165 struct rtw89_core_tx_request {
1166 	enum rtw89_core_tx_type tx_type;
1167 
1168 	struct sk_buff *skb;
1169 	struct ieee80211_vif *vif;
1170 	struct ieee80211_sta *sta;
1171 	struct rtw89_tx_desc_info desc_info;
1172 };
1173 
1174 struct rtw89_txq {
1175 	struct list_head list;
1176 	unsigned long flags;
1177 	int wait_cnt;
1178 };
1179 
1180 struct rtw89_mac_ax_gnt {
1181 	u8 gnt_bt_sw_en;
1182 	u8 gnt_bt;
1183 	u8 gnt_wl_sw_en;
1184 	u8 gnt_wl;
1185 } __packed;
1186 
1187 struct rtw89_mac_ax_wl_act {
1188 	u8 wlan_act_en;
1189 	u8 wlan_act;
1190 };
1191 
1192 #define RTW89_MAC_AX_COEX_GNT_NR 2
1193 struct rtw89_mac_ax_coex_gnt {
1194 	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1195 	struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1196 };
1197 
1198 enum rtw89_btc_ncnt {
1199 	BTC_NCNT_POWER_ON = 0x0,
1200 	BTC_NCNT_POWER_OFF,
1201 	BTC_NCNT_INIT_COEX,
1202 	BTC_NCNT_SCAN_START,
1203 	BTC_NCNT_SCAN_FINISH,
1204 	BTC_NCNT_SPECIAL_PACKET,
1205 	BTC_NCNT_SWITCH_BAND,
1206 	BTC_NCNT_RFK_TIMEOUT,
1207 	BTC_NCNT_SHOW_COEX_INFO,
1208 	BTC_NCNT_ROLE_INFO,
1209 	BTC_NCNT_CONTROL,
1210 	BTC_NCNT_RADIO_STATE,
1211 	BTC_NCNT_CUSTOMERIZE,
1212 	BTC_NCNT_WL_RFK,
1213 	BTC_NCNT_WL_STA,
1214 	BTC_NCNT_WL_STA_LAST,
1215 	BTC_NCNT_FWINFO,
1216 	BTC_NCNT_TIMER,
1217 	BTC_NCNT_SWITCH_CHBW,
1218 	BTC_NCNT_RESUME_DL_FW,
1219 	BTC_NCNT_COUNTRYCODE,
1220 	BTC_NCNT_NUM,
1221 };
1222 
1223 enum rtw89_btc_btinfo {
1224 	BTC_BTINFO_L0 = 0,
1225 	BTC_BTINFO_L1,
1226 	BTC_BTINFO_L2,
1227 	BTC_BTINFO_L3,
1228 	BTC_BTINFO_H0,
1229 	BTC_BTINFO_H1,
1230 	BTC_BTINFO_H2,
1231 	BTC_BTINFO_H3,
1232 	BTC_BTINFO_MAX
1233 };
1234 
1235 enum rtw89_btc_dcnt {
1236 	BTC_DCNT_RUN = 0x0,
1237 	BTC_DCNT_CX_RUNINFO,
1238 	BTC_DCNT_RPT,
1239 	BTC_DCNT_RPT_HANG,
1240 	BTC_DCNT_CYCLE,
1241 	BTC_DCNT_CYCLE_HANG,
1242 	BTC_DCNT_W1,
1243 	BTC_DCNT_W1_HANG,
1244 	BTC_DCNT_B1,
1245 	BTC_DCNT_B1_HANG,
1246 	BTC_DCNT_TDMA_NONSYNC,
1247 	BTC_DCNT_SLOT_NONSYNC,
1248 	BTC_DCNT_BTCNT_HANG,
1249 	BTC_DCNT_BTTX_HANG,
1250 	BTC_DCNT_WL_SLOT_DRIFT,
1251 	BTC_DCNT_WL_STA_LAST,
1252 	BTC_DCNT_BT_SLOT_DRIFT,
1253 	BTC_DCNT_BT_SLOT_FLOOD,
1254 	BTC_DCNT_FDDT_TRIG,
1255 	BTC_DCNT_E2G,
1256 	BTC_DCNT_E2G_HANG,
1257 	BTC_DCNT_WL_FW_VER_MATCH,
1258 	BTC_DCNT_NULL_TX_FAIL,
1259 	BTC_DCNT_WL_STA_NTFY,
1260 	BTC_DCNT_NUM,
1261 };
1262 
1263 enum rtw89_btc_wl_state_cnt {
1264 	BTC_WCNT_SCANAP = 0x0,
1265 	BTC_WCNT_DHCP,
1266 	BTC_WCNT_EAPOL,
1267 	BTC_WCNT_ARP,
1268 	BTC_WCNT_SCBDUPDATE,
1269 	BTC_WCNT_RFK_REQ,
1270 	BTC_WCNT_RFK_GO,
1271 	BTC_WCNT_RFK_REJECT,
1272 	BTC_WCNT_RFK_TIMEOUT,
1273 	BTC_WCNT_CH_UPDATE,
1274 	BTC_WCNT_DBCC_ALL_2G,
1275 	BTC_WCNT_DBCC_CHG,
1276 	BTC_WCNT_RX_OK_LAST,
1277 	BTC_WCNT_RX_OK_LAST2S,
1278 	BTC_WCNT_RX_ERR_LAST,
1279 	BTC_WCNT_RX_ERR_LAST2S,
1280 	BTC_WCNT_RX_LAST,
1281 	BTC_WCNT_NUM
1282 };
1283 
1284 enum rtw89_btc_bt_state_cnt {
1285 	BTC_BCNT_RETRY = 0x0,
1286 	BTC_BCNT_REINIT,
1287 	BTC_BCNT_REENABLE,
1288 	BTC_BCNT_SCBDREAD,
1289 	BTC_BCNT_RELINK,
1290 	BTC_BCNT_IGNOWL,
1291 	BTC_BCNT_INQPAG,
1292 	BTC_BCNT_INQ,
1293 	BTC_BCNT_PAGE,
1294 	BTC_BCNT_ROLESW,
1295 	BTC_BCNT_AFH,
1296 	BTC_BCNT_INFOUPDATE,
1297 	BTC_BCNT_INFOSAME,
1298 	BTC_BCNT_SCBDUPDATE,
1299 	BTC_BCNT_HIPRI_TX,
1300 	BTC_BCNT_HIPRI_RX,
1301 	BTC_BCNT_LOPRI_TX,
1302 	BTC_BCNT_LOPRI_RX,
1303 	BTC_BCNT_POLUT,
1304 	BTC_BCNT_POLUT_NOW,
1305 	BTC_BCNT_POLUT_DIFF,
1306 	BTC_BCNT_RATECHG,
1307 	BTC_BCNT_NUM,
1308 };
1309 
1310 enum rtw89_btc_bt_profile {
1311 	BTC_BT_NOPROFILE = 0,
1312 	BTC_BT_HFP = BIT(0),
1313 	BTC_BT_HID = BIT(1),
1314 	BTC_BT_A2DP = BIT(2),
1315 	BTC_BT_PAN = BIT(3),
1316 	BTC_PROFILE_MAX = 4,
1317 };
1318 
1319 struct rtw89_btc_ant_info {
1320 	u8 type;  /* shared, dedicated */
1321 	u8 num;
1322 	u8 isolation;
1323 
1324 	u8 single_pos: 1;/* Single antenna at S0 or S1 */
1325 	u8 diversity: 1;
1326 	u8 btg_pos: 2;
1327 	u8 stream_cnt: 4;
1328 };
1329 
1330 struct rtw89_btc_ant_info_v7 {
1331 	u8 type;  /* shared, dedicated(non-shared) */
1332 	u8 num;   /* antenna count  */
1333 	u8 isolation;
1334 	u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1335 
1336 	u8 diversity; /* only for wifi use 1-antenna */
1337 	u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1338 	u8 stream_cnt;  /* spatial_stream count */
1339 	u8 rsvd;
1340 } __packed;
1341 
1342 enum rtw89_tfc_dir {
1343 	RTW89_TFC_UL,
1344 	RTW89_TFC_DL,
1345 };
1346 
1347 struct rtw89_btc_wl_smap {
1348 	u32 busy: 1;
1349 	u32 scan: 1;
1350 	u32 connecting: 1;
1351 	u32 roaming: 1;
1352 	u32 dbccing: 1;
1353 	u32 transacting: 1;
1354 	u32 _4way: 1;
1355 	u32 rf_off: 1;
1356 	u32 lps: 2;
1357 	u32 ips: 1;
1358 	u32 init_ok: 1;
1359 	u32 traffic_dir : 2;
1360 	u32 rf_off_pre: 1;
1361 	u32 lps_pre: 2;
1362 	u32 lps_exiting: 1;
1363 	u32 emlsr: 1;
1364 };
1365 
1366 enum rtw89_tfc_lv {
1367 	RTW89_TFC_IDLE,
1368 	RTW89_TFC_ULTRA_LOW,
1369 	RTW89_TFC_LOW,
1370 	RTW89_TFC_MID,
1371 	RTW89_TFC_HIGH,
1372 };
1373 
1374 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1375 DECLARE_EWMA(tp, 10, 2);
1376 
1377 struct rtw89_traffic_stats {
1378 	/* units in bytes */
1379 	u64 tx_unicast;
1380 	u64 rx_unicast;
1381 	u32 tx_avg_len;
1382 	u32 rx_avg_len;
1383 
1384 	/* count for packets */
1385 	u64 tx_cnt;
1386 	u64 rx_cnt;
1387 
1388 	/* units in Mbps */
1389 	u32 tx_throughput;
1390 	u32 rx_throughput;
1391 	u32 tx_throughput_raw;
1392 	u32 rx_throughput_raw;
1393 
1394 	u32 rx_tf_acc;
1395 	u32 rx_tf_periodic;
1396 
1397 	enum rtw89_tfc_lv tx_tfc_lv;
1398 	enum rtw89_tfc_lv rx_tfc_lv;
1399 	struct ewma_tp tx_ewma_tp;
1400 	struct ewma_tp rx_ewma_tp;
1401 
1402 	u16 tx_rate;
1403 	u16 rx_rate;
1404 };
1405 
1406 struct rtw89_btc_chdef {
1407 	u8 center_ch;
1408 	u8 band;
1409 	u8 chan;
1410 	enum rtw89_sc_offset offset;
1411 	enum rtw89_bandwidth bw;
1412 };
1413 
1414 struct rtw89_btc_statistic {
1415 	u8 rssi; /* 0%~110% (dBm = rssi -110) */
1416 	struct rtw89_traffic_stats traffic;
1417 };
1418 
1419 #define BTC_WL_RSSI_THMAX 4
1420 
1421 struct rtw89_btc_wl_link_info {
1422 	struct rtw89_btc_chdef chdef;
1423 	struct rtw89_btc_statistic stat;
1424 	enum rtw89_tfc_dir dir;
1425 	u8 rssi_state[BTC_WL_RSSI_THMAX];
1426 	u8 mac_addr[ETH_ALEN];
1427 	u8 busy;
1428 	u8 ch;
1429 	u8 bw;
1430 	u8 band;
1431 	u8 role;
1432 	u8 pid;
1433 	u8 phy;
1434 	u8 dtim_period;
1435 	u8 mode;
1436 	u8 tx_1ss_limit;
1437 
1438 	u8 mac_id;
1439 	u8 tx_retry;
1440 
1441 	u32 bcn_period;
1442 	u32 busy_t;
1443 	u32 tx_time;
1444 	u32 client_cnt;
1445 	u32 rx_rate_drop_cnt;
1446 	u32 noa_duration;
1447 
1448 	u32 active: 1;
1449 	u32 noa: 1;
1450 	u32 client_ps: 1;
1451 	u32 connected: 2;
1452 };
1453 
1454 union rtw89_btc_wl_state_map {
1455 	u32 val;
1456 	struct rtw89_btc_wl_smap map;
1457 };
1458 
1459 struct rtw89_btc_bt_hfp_desc {
1460 	u32 exist: 1;
1461 	u32 type: 2;
1462 	u32 rsvd: 29;
1463 };
1464 
1465 struct rtw89_btc_bt_hid_desc {
1466 	u32 exist: 1;
1467 	u32 slot_info: 2;
1468 	u32 pair_cnt: 2;
1469 	u32 type: 8;
1470 	u32 rsvd: 19;
1471 };
1472 
1473 struct rtw89_btc_bt_a2dp_desc {
1474 	u8 exist: 1;
1475 	u8 exist_last: 1;
1476 	u8 play_latency: 1;
1477 	u8 type: 3;
1478 	u8 active: 1;
1479 	u8 sink: 1;
1480 	u32 handle_update: 1;
1481 	u32 devinfo_query: 1;
1482 	u32 no_empty_streak_2s: 8;
1483 	u32 no_empty_streak_max: 8;
1484 	u32 rsvd: 6;
1485 
1486 	u8 bitpool;
1487 	u16 vendor_id;
1488 	u32 device_name;
1489 	u32 flush_time;
1490 };
1491 
1492 struct rtw89_btc_bt_pan_desc {
1493 	u32 exist: 1;
1494 	u32 type: 1;
1495 	u32 active: 1;
1496 	u32 rsvd: 29;
1497 };
1498 
1499 struct rtw89_btc_bt_rfk_info {
1500 	u32 run: 1;
1501 	u32 req: 1;
1502 	u32 timeout: 1;
1503 	u32 rsvd: 29;
1504 };
1505 
1506 union rtw89_btc_bt_rfk_info_map {
1507 	u32 val;
1508 	struct rtw89_btc_bt_rfk_info map;
1509 };
1510 
1511 struct rtw89_btc_bt_ver_info {
1512 	u32 fw_coex; /* match with which coex_ver */
1513 	u32 fw;
1514 };
1515 
1516 struct rtw89_btc_bool_sta_chg {
1517 	u32 now: 1;
1518 	u32 last: 1;
1519 	u32 remain: 1;
1520 	u32 srvd: 29;
1521 };
1522 
1523 struct rtw89_btc_u8_sta_chg {
1524 	u8 now;
1525 	u8 last;
1526 	u8 remain;
1527 	u8 rsvd;
1528 };
1529 
1530 struct rtw89_btc_wl_scan_info {
1531 	u8 band[RTW89_PHY_MAX];
1532 	u8 phy_map;
1533 	u8 rsvd;
1534 };
1535 
1536 struct rtw89_btc_wl_dbcc_info {
1537 	u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1538 	u8 scan_band[RTW89_PHY_MAX]; /* scan band in  each phy */
1539 	u8 real_band[RTW89_PHY_MAX];
1540 	u8 role[RTW89_PHY_MAX]; /* role in each phy */
1541 };
1542 
1543 struct rtw89_btc_wl_active_role {
1544 	u8 connected: 1;
1545 	u8 pid: 3;
1546 	u8 phy: 1;
1547 	u8 noa: 1;
1548 	u8 band: 2;
1549 
1550 	u8 client_ps: 1;
1551 	u8 bw: 7;
1552 
1553 	u8 role;
1554 	u8 ch;
1555 
1556 	u16 tx_lvl;
1557 	u16 rx_lvl;
1558 	u16 tx_rate;
1559 	u16 rx_rate;
1560 };
1561 
1562 struct rtw89_btc_wl_active_role_v1 {
1563 	u8 connected: 1;
1564 	u8 pid: 3;
1565 	u8 phy: 1;
1566 	u8 noa: 1;
1567 	u8 band: 2;
1568 
1569 	u8 client_ps: 1;
1570 	u8 bw: 7;
1571 
1572 	u8 role;
1573 	u8 ch;
1574 
1575 	u16 tx_lvl;
1576 	u16 rx_lvl;
1577 	u16 tx_rate;
1578 	u16 rx_rate;
1579 
1580 	u32 noa_duration; /* ms */
1581 };
1582 
1583 struct rtw89_btc_wl_active_role_v2 {
1584 	u8 connected: 1;
1585 	u8 pid: 3;
1586 	u8 phy: 1;
1587 	u8 noa: 1;
1588 	u8 band: 2;
1589 
1590 	u8 client_ps: 1;
1591 	u8 bw: 7;
1592 
1593 	u8 role;
1594 	u8 ch;
1595 
1596 	u32 noa_duration; /* ms */
1597 };
1598 
1599 struct rtw89_btc_wl_active_role_v7 {
1600 	u8 connected;
1601 	u8 pid;
1602 	u8 phy;
1603 	u8 noa;
1604 
1605 	u8 band;
1606 	u8 client_ps;
1607 	u8 bw;
1608 	u8 role;
1609 
1610 	u8 ch;
1611 	u8 noa_dur;
1612 	u8 client_cnt;
1613 	u8 rsvd2;
1614 } __packed;
1615 
1616 struct rtw89_btc_wl_role_info_bpos {
1617 	u16 none: 1;
1618 	u16 station: 1;
1619 	u16 ap: 1;
1620 	u16 vap: 1;
1621 	u16 adhoc: 1;
1622 	u16 adhoc_master: 1;
1623 	u16 mesh: 1;
1624 	u16 moniter: 1;
1625 	u16 p2p_device: 1;
1626 	u16 p2p_gc: 1;
1627 	u16 p2p_go: 1;
1628 	u16 nan: 1;
1629 };
1630 
1631 struct rtw89_btc_wl_scc_ctrl {
1632 	u8 null_role1;
1633 	u8 null_role2;
1634 	u8 ebt_null; /* if tx null at EBT slot */
1635 };
1636 
1637 union rtw89_btc_wl_role_info_map {
1638 	u16 val;
1639 	struct rtw89_btc_wl_role_info_bpos role;
1640 };
1641 
1642 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1643 	u8 connect_cnt;
1644 	u8 link_mode;
1645 	union rtw89_btc_wl_role_info_map role_map;
1646 	struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1647 };
1648 
1649 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1650 	u8 connect_cnt;
1651 	u8 link_mode;
1652 	union rtw89_btc_wl_role_info_map role_map;
1653 	struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1654 	u32 mrole_type; /* btc_wl_mrole_type */
1655 	u32 mrole_noa_duration; /* ms */
1656 
1657 	u32 dbcc_en: 1;
1658 	u32 dbcc_chg: 1;
1659 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1660 	u32 link_mode_chg: 1;
1661 	u32 rsvd: 27;
1662 };
1663 
1664 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1665 	u8 connect_cnt;
1666 	u8 link_mode;
1667 	union rtw89_btc_wl_role_info_map role_map;
1668 	struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1669 	u32 mrole_type; /* btc_wl_mrole_type */
1670 	u32 mrole_noa_duration; /* ms */
1671 
1672 	u32 dbcc_en: 1;
1673 	u32 dbcc_chg: 1;
1674 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1675 	u32 link_mode_chg: 1;
1676 	u32 rsvd: 27;
1677 };
1678 
1679 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1680 	u8 connected;
1681 	u8 pid;
1682 	u8 phy;
1683 	u8 noa;
1684 
1685 	u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1686 	u8 active; /* 0:rlink is under doze */
1687 	u8 bw; /* enum channel_width */
1688 	u8 role; /*enum role_type */
1689 
1690 	u8 ch;
1691 	u8 noa_dur; /* ms */
1692 	u8 client_cnt; /* for Role = P2P-Go/AP */
1693 	u8 mode; /* wifi protocol */
1694 } __packed;
1695 
1696 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1697 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1698 	u8 connect_cnt;
1699 	u8 link_mode;
1700 	u8 link_mode_chg;
1701 	u8 p2p_2g;
1702 
1703 	struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1704 
1705 	u32 role_map;
1706 	u32 mrole_type; /* btc_wl_mrole_type */
1707 	u32 mrole_noa_duration; /* ms */
1708 	u32 dbcc_en;
1709 	u32 dbcc_chg;
1710 	u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1711 } __packed;
1712 
1713 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1714 	u8 connect_cnt;
1715 	u8 link_mode;
1716 	u8 link_mode_chg;
1717 	u8 p2p_2g;
1718 
1719 	u8 pta_req_band;
1720 	u8 dbcc_en; /* 1+1 and 2.4G-included */
1721 	u8 dbcc_chg;
1722 	u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1723 
1724 	struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1725 
1726 	u32 role_map;
1727 	u32 mrole_type; /* btc_wl_mrole_type */
1728 	u32 mrole_noa_duration; /* ms */
1729 } __packed;
1730 
1731 struct rtw89_btc_wl_ver_info {
1732 	u32 fw_coex; /* match with which coex_ver */
1733 	u32 fw;
1734 	u32 mac;
1735 	u32 bb;
1736 	u32 rf;
1737 };
1738 
1739 struct rtw89_btc_wl_afh_info {
1740 	u8 en;
1741 	u8 ch;
1742 	u8 bw;
1743 	u8 rsvd;
1744 } __packed;
1745 
1746 struct rtw89_btc_wl_rfk_info {
1747 	u32 state: 2;
1748 	u32 path_map: 4;
1749 	u32 phy_map: 2;
1750 	u32 band: 2;
1751 	u32 type: 8;
1752 	u32 rsvd: 14;
1753 
1754 	u32 start_time;
1755 	u32 proc_time;
1756 };
1757 
1758 struct rtw89_btc_bt_smap {
1759 	u32 connect: 1;
1760 	u32 ble_connect: 1;
1761 	u32 acl_busy: 1;
1762 	u32 sco_busy: 1;
1763 	u32 mesh_busy: 1;
1764 	u32 inq_pag: 1;
1765 };
1766 
1767 union rtw89_btc_bt_state_map {
1768 	u32 val;
1769 	struct rtw89_btc_bt_smap map;
1770 };
1771 
1772 #define BTC_BT_RSSI_THMAX 4
1773 #define BTC_BT_AFH_GROUP 12
1774 #define BTC_BT_AFH_LE_GROUP 5
1775 
1776 struct rtw89_btc_bt_link_info {
1777 	struct rtw89_btc_u8_sta_chg profile_cnt;
1778 	struct rtw89_btc_bool_sta_chg multi_link;
1779 	struct rtw89_btc_bool_sta_chg relink;
1780 	struct rtw89_btc_bt_hfp_desc hfp_desc;
1781 	struct rtw89_btc_bt_hid_desc hid_desc;
1782 	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1783 	struct rtw89_btc_bt_pan_desc pan_desc;
1784 	union rtw89_btc_bt_state_map status;
1785 
1786 	u8 sut_pwr_level[BTC_PROFILE_MAX];
1787 	u8 golden_rx_shift[BTC_PROFILE_MAX];
1788 	u8 rssi_state[BTC_BT_RSSI_THMAX];
1789 	u8 afh_map[BTC_BT_AFH_GROUP];
1790 	u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1791 
1792 	u32 role_sw: 1;
1793 	u32 slave_role: 1;
1794 	u32 afh_update: 1;
1795 	u32 cqddr: 1;
1796 	u32 rssi: 8;
1797 	u32 tx_3m: 1;
1798 	u32 rsvd: 19;
1799 };
1800 
1801 struct rtw89_btc_3rdcx_info {
1802 	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1803 	u8 hw_coex;
1804 	u16 rsvd;
1805 };
1806 
1807 struct rtw89_btc_dm_emap {
1808 	u32 init: 1;
1809 	u32 pta_owner: 1;
1810 	u32 wl_rfk_timeout: 1;
1811 	u32 bt_rfk_timeout: 1;
1812 	u32 wl_fw_hang: 1;
1813 	u32 cycle_hang: 1;
1814 	u32 w1_hang: 1;
1815 	u32 b1_hang: 1;
1816 	u32 tdma_no_sync: 1;
1817 	u32 slot_no_sync: 1;
1818 	u32 wl_slot_drift: 1;
1819 	u32 bt_slot_drift: 1;
1820 	u32 role_num_mismatch: 1;
1821 	u32 null1_tx_late: 1;
1822 	u32 bt_afh_conflict: 1;
1823 	u32 bt_leafh_conflict: 1;
1824 	u32 bt_slot_flood: 1;
1825 	u32 wl_e2g_hang: 1;
1826 	u32 wl_ver_mismatch: 1;
1827 	u32 bt_ver_mismatch: 1;
1828 	u32 rfe_type0: 1;
1829 	u32 h2c_buffer_over: 1;
1830 	u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1831 	u32 wl_no_sta_ntfy: 1;
1832 
1833 	u32 h2c_bmap_mismatch: 1;
1834 	u32 c2h_bmap_mismatch: 1;
1835 	u32 h2c_struct_invalid: 1;
1836 	u32 c2h_struct_invalid: 1;
1837 	u32 h2c_c2h_buffer_mismatch: 1;
1838 };
1839 
1840 union rtw89_btc_dm_error_map {
1841 	u32 val;
1842 	struct rtw89_btc_dm_emap map;
1843 };
1844 
1845 struct rtw89_btc_rf_para {
1846 	u32 tx_pwr_freerun;
1847 	u32 rx_gain_freerun;
1848 	u32 tx_pwr_perpkt;
1849 	u32 rx_gain_perpkt;
1850 };
1851 
1852 struct rtw89_btc_wl_nhm {
1853 	u8 instant_wl_nhm_dbm;
1854 	u8 instant_wl_nhm_per_mhz;
1855 	u16 valid_record_times;
1856 	s8 record_pwr[16];
1857 	u8 record_ratio[16];
1858 	s8 pwr; /* dbm_per_MHz  */
1859 	u8 ratio;
1860 	u8 current_status;
1861 	u8 refresh;
1862 	bool start_flag;
1863 	s8 pwr_max;
1864 	s8 pwr_min;
1865 };
1866 
1867 struct rtw89_btc_wl_info {
1868 	struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1869 	struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1870 	struct rtw89_btc_wl_rfk_info rfk_info;
1871 	struct rtw89_btc_wl_ver_info  ver_info;
1872 	struct rtw89_btc_wl_afh_info afh_info;
1873 	struct rtw89_btc_wl_role_info role_info;
1874 	struct rtw89_btc_wl_role_info_v1 role_info_v1;
1875 	struct rtw89_btc_wl_role_info_v2 role_info_v2;
1876 	struct rtw89_btc_wl_role_info_v7 role_info_v7;
1877 	struct rtw89_btc_wl_role_info_v8 role_info_v8;
1878 	struct rtw89_btc_wl_scan_info scan_info;
1879 	struct rtw89_btc_wl_dbcc_info dbcc_info;
1880 	struct rtw89_btc_rf_para rf_para;
1881 	struct rtw89_btc_wl_nhm nhm;
1882 	union rtw89_btc_wl_state_map status;
1883 
1884 	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1885 	u8 rssi_level;
1886 	u8 cn_report;
1887 	u8 coex_mode;
1888 	u8 pta_req_mac;
1889 	u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1  */
1890 
1891 	bool is_5g_hi_channel;
1892 	bool pta_reg_mac_chg;
1893 	bool bg_mode;
1894 	bool he_mode;
1895 	bool scbd_change;
1896 	bool fw_ver_mismatch;
1897 	bool client_cnt_inc_2g;
1898 	u32 scbd;
1899 };
1900 
1901 struct rtw89_btc_module {
1902 	struct rtw89_btc_ant_info ant;
1903 	u8 rfe_type;
1904 	u8 cv;
1905 
1906 	u8 bt_solo: 1;
1907 	u8 bt_pos: 1;
1908 	u8 switch_type: 1;
1909 	u8 wa_type: 3;
1910 
1911 	u8 kt_ver_adie;
1912 };
1913 
1914 struct rtw89_btc_module_v7 {
1915 	u8 rfe_type;
1916 	u8 kt_ver;
1917 	u8 bt_solo;
1918 	u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1919 
1920 	u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1921 	u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1922 	u8 kt_ver_adie;
1923 	u8 rsvd;
1924 
1925 	struct rtw89_btc_ant_info_v7 ant;
1926 } __packed;
1927 
1928 union rtw89_btc_module_info {
1929 	struct rtw89_btc_module md;
1930 	struct rtw89_btc_module_v7 md_v7;
1931 };
1932 
1933 #define RTW89_BTC_DM_MAXSTEP 30
1934 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1935 
1936 struct rtw89_btc_dm_step {
1937 	u16 step[RTW89_BTC_DM_MAXSTEP];
1938 	u8 step_pos;
1939 	bool step_ov;
1940 };
1941 
1942 struct rtw89_btc_init_info {
1943 	struct rtw89_btc_module module;
1944 	u8 wl_guard_ch;
1945 
1946 	u8 wl_only: 1;
1947 	u8 wl_init_ok: 1;
1948 	u8 dbcc_en: 1;
1949 	u8 cx_other: 1;
1950 	u8 bt_only: 1;
1951 
1952 	u16 rsvd;
1953 };
1954 
1955 struct rtw89_btc_init_info_v7 {
1956 	u8 wl_guard_ch;
1957 	u8 wl_only;
1958 	u8 wl_init_ok;
1959 	u8 rsvd3;
1960 
1961 	u8 cx_other;
1962 	u8 bt_only;
1963 	u8 pta_mode;
1964 	u8 pta_direction;
1965 
1966 	struct rtw89_btc_module_v7 module;
1967 } __packed;
1968 
1969 union rtw89_btc_init_info_u {
1970 	struct rtw89_btc_init_info init;
1971 	struct rtw89_btc_init_info_v7 init_v7;
1972 };
1973 
1974 struct rtw89_btc_wl_tx_limit_para {
1975 	u16 enable;
1976 	u32 tx_time;	/* unit: us */
1977 	u16 tx_retry;
1978 };
1979 
1980 enum rtw89_btc_bt_scan_type {
1981 	BTC_SCAN_INQ	= 0,
1982 	BTC_SCAN_PAGE,
1983 	BTC_SCAN_BLE,
1984 	BTC_SCAN_INIT,
1985 	BTC_SCAN_TV,
1986 	BTC_SCAN_ADV,
1987 	BTC_SCAN_MAX1,
1988 };
1989 
1990 enum rtw89_btc_ble_scan_type {
1991 	CXSCAN_BG = 0,
1992 	CXSCAN_INIT,
1993 	CXSCAN_LE,
1994 	CXSCAN_MAX
1995 };
1996 
1997 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1998 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1999 
2000 struct rtw89_btc_bt_scan_info_v1 {
2001 	__le16 win;
2002 	__le16 intvl;
2003 	__le32 flags;
2004 } __packed;
2005 
2006 struct rtw89_btc_bt_scan_info_v2 {
2007 	__le16 win;
2008 	__le16 intvl;
2009 } __packed;
2010 
2011 struct rtw89_btc_fbtc_btscan_v1 {
2012 	u8 fver; /* btc_ver::fcxbtscan */
2013 	u8 rsvd;
2014 	__le16 rsvd2;
2015 	struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2016 } __packed;
2017 
2018 struct rtw89_btc_fbtc_btscan_v2 {
2019 	u8 fver; /* btc_ver::fcxbtscan */
2020 	u8 type;
2021 	__le16 rsvd2;
2022 	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2023 } __packed;
2024 
2025 struct rtw89_btc_fbtc_btscan_v7 {
2026 	u8 fver; /* btc_ver::fcxbtscan */
2027 	u8 type;
2028 	u8 rsvd0;
2029 	u8 rsvd1;
2030 	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2031 } __packed;
2032 
2033 union rtw89_btc_fbtc_btscan {
2034 	struct rtw89_btc_fbtc_btscan_v1 v1;
2035 	struct rtw89_btc_fbtc_btscan_v2 v2;
2036 	struct rtw89_btc_fbtc_btscan_v7 v7;
2037 };
2038 
2039 struct rtw89_btc_bt_info {
2040 	struct rtw89_btc_bt_link_info link_info;
2041 	struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2042 	struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2043 	struct rtw89_btc_bt_ver_info ver_info;
2044 	struct rtw89_btc_bool_sta_chg enable;
2045 	struct rtw89_btc_bool_sta_chg inq_pag;
2046 	struct rtw89_btc_rf_para rf_para;
2047 	union rtw89_btc_bt_rfk_info_map rfk_info;
2048 
2049 	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2050 	u8 rssi_level;
2051 
2052 	u32 scbd;
2053 	u32 feature;
2054 
2055 	u32 mbx_avl: 1;
2056 	u32 whql_test: 1;
2057 	u32 igno_wl: 1;
2058 	u32 reinit: 1;
2059 	u32 ble_scan_en: 1;
2060 	u32 btg_type: 1;
2061 	u32 inq: 1;
2062 	u32 pag: 1;
2063 	u32 run_patch_code: 1;
2064 	u32 hi_lna_rx: 1;
2065 	u32 scan_rx_low_pri: 1;
2066 	u32 scan_info_update: 1;
2067 	u32 lna_constrain: 3;
2068 	u32 rsvd: 17;
2069 };
2070 
2071 struct rtw89_btc_cx {
2072 	struct rtw89_btc_wl_info wl;
2073 	struct rtw89_btc_bt_info bt;
2074 	struct rtw89_btc_3rdcx_info other;
2075 	u32 state_map;
2076 	u32 cnt_bt[BTC_BCNT_NUM];
2077 	u32 cnt_wl[BTC_WCNT_NUM];
2078 };
2079 
2080 struct rtw89_btc_fbtc_tdma {
2081 	u8 type; /* btc_ver::fcxtdma */
2082 	u8 rxflctrl;
2083 	u8 txpause;
2084 	u8 wtgle_n;
2085 	u8 leak_n;
2086 	u8 ext_ctrl;
2087 	u8 rxflctrl_role;
2088 	u8 option_ctrl;
2089 } __packed;
2090 
2091 struct rtw89_btc_fbtc_tdma_v3 {
2092 	u8 fver; /* btc_ver::fcxtdma */
2093 	u8 rsvd;
2094 	__le16 rsvd1;
2095 	struct rtw89_btc_fbtc_tdma tdma;
2096 } __packed;
2097 
2098 union rtw89_btc_fbtc_tdma_le32 {
2099 	struct rtw89_btc_fbtc_tdma v1;
2100 	struct rtw89_btc_fbtc_tdma_v3 v3;
2101 };
2102 
2103 #define CXMREG_MAX 30
2104 #define CXMREG_MAX_V2 20
2105 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2106 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2107 
2108 enum rtw89_btc_bt_sta_counter {
2109 	BTC_BCNT_RFK_REQ = 0,
2110 	BTC_BCNT_RFK_GO = 1,
2111 	BTC_BCNT_RFK_REJECT = 2,
2112 	BTC_BCNT_RFK_FAIL = 3,
2113 	BTC_BCNT_RFK_TIMEOUT = 4,
2114 	BTC_BCNT_HI_TX = 5,
2115 	BTC_BCNT_HI_RX = 6,
2116 	BTC_BCNT_LO_TX = 7,
2117 	BTC_BCNT_LO_RX = 8,
2118 	BTC_BCNT_POLLUTED = 9,
2119 	BTC_BCNT_STA_MAX
2120 };
2121 
2122 enum rtw89_btc_bt_sta_counter_v105 {
2123 	BTC_BCNT_RFK_REQ_V105 = 0,
2124 	BTC_BCNT_HI_TX_V105 = 1,
2125 	BTC_BCNT_HI_RX_V105 = 2,
2126 	BTC_BCNT_LO_TX_V105 = 3,
2127 	BTC_BCNT_LO_RX_V105 = 4,
2128 	BTC_BCNT_POLLUTED_V105 = 5,
2129 	BTC_BCNT_STA_MAX_V105
2130 };
2131 
2132 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2133 	u16 fver; /* btc_ver::fcxbtcrpt */
2134 	u16 rpt_cnt; /* tmr counters */
2135 	u32 wl_fw_coex_ver; /* match which driver's coex version */
2136 	u32 wl_fw_cx_offload;
2137 	u32 wl_fw_ver;
2138 	u32 rpt_enable;
2139 	u32 rpt_para; /* ms */
2140 	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2141 	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2142 	u32 mb_recv_cnt; /* fw recv mailbox counter */
2143 	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2144 	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2145 	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2146 	u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2147 	u32 c2h_cnt; /* fw send c2h counter  */
2148 	u32 h2c_cnt; /* fw recv h2c counter */
2149 } __packed;
2150 
2151 struct rtw89_btc_fbtc_rpt_ctrl_info {
2152 	__le32 cnt; /* fw report counter */
2153 	__le32 en; /* report map */
2154 	__le32 para; /* not used */
2155 
2156 	__le32 cnt_c2h; /* fw send c2h counter  */
2157 	__le32 cnt_h2c; /* fw recv h2c counter */
2158 	__le32 len_c2h; /* The total length of the last C2H  */
2159 
2160 	__le32 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2161 	__le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2162 } __packed;
2163 
2164 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2165 	__le32 cx_ver; /* match which driver's coex version */
2166 	__le32 fw_ver;
2167 	__le32 en; /* report map */
2168 
2169 	__le16 cnt; /* fw report counter */
2170 	__le16 cnt_c2h; /* fw send c2h counter  */
2171 	__le16 cnt_h2c; /* fw recv h2c counter */
2172 	__le16 len_c2h; /* The total length of the last C2H  */
2173 
2174 	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2175 	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2176 } __packed;
2177 
2178 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2179 	__le16 cnt; /* fw report counter */
2180 	__le16 cnt_c2h; /* fw send c2h counter  */
2181 	__le16 cnt_h2c; /* fw recv h2c counter */
2182 	__le16 len_c2h; /* The total length of the last C2H  */
2183 
2184 	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
2185 	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2186 
2187 	__le32 cx_ver; /* match which driver's coex version */
2188 	__le32 fw_ver;
2189 	__le32 en; /* report map */
2190 } __packed;
2191 
2192 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2193 	__le32 cx_ver; /* match which driver's coex version */
2194 	__le32 cx_offload;
2195 	__le32 fw_ver;
2196 } __packed;
2197 
2198 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2199 	__le32 cnt_empty; /* a2dp empty count */
2200 	__le32 cnt_flowctrl; /* a2dp empty flow control counter */
2201 	__le32 cnt_tx;
2202 	__le32 cnt_ack;
2203 	__le32 cnt_nack;
2204 } __packed;
2205 
2206 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2207 	__le32 cnt_send_ok; /* fw send mailbox ok counter */
2208 	__le32 cnt_send_fail; /* fw send mailbox fail counter */
2209 	__le32 cnt_recv; /* fw recv mailbox counter */
2210 	struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2211 } __packed;
2212 
2213 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2214 	u8 fver;
2215 	u8 rsvd;
2216 	__le16 rsvd1;
2217 	struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2218 	struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2219 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2220 	__le32 bt_cnt[BTC_BCNT_STA_MAX];
2221 	struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
2222 } __packed;
2223 
2224 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2225 	u8 fver;
2226 	u8 rsvd;
2227 	__le16 rsvd1;
2228 
2229 	u8 gnt_val[RTW89_PHY_MAX][4];
2230 	__le16 bt_cnt[BTC_BCNT_STA_MAX];
2231 
2232 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2233 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2234 } __packed;
2235 
2236 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2237 	u8 fver;
2238 	u8 rsvd;
2239 	__le16 rsvd1;
2240 
2241 	u8 gnt_val[RTW89_PHY_MAX][4];
2242 	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2243 
2244 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2245 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2246 } __packed;
2247 
2248 struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2249 	u8 fver;
2250 	u8 rsvd0;
2251 	u8 rsvd1;
2252 	u8 rsvd2;
2253 
2254 	u8 gnt_val[RTW89_PHY_MAX][4];
2255 	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2256 
2257 	struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2258 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2259 } __packed;
2260 
2261 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2262 	u8 fver;
2263 	u8 rsvd0;
2264 	u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2265 	u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2266 
2267 	u8 gnt_val[RTW89_PHY_MAX][4];
2268 	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2269 
2270 	struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2271 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2272 } __packed;
2273 
2274 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2275 	struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2276 	struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2277 	struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2278 	struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2279 	struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2280 	struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2281 };
2282 
2283 enum rtw89_fbtc_ext_ctrl_type {
2284 	CXECTL_OFF = 0x0, /* tdma off */
2285 	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2286 	CXECTL_EXT = 0x2,
2287 	CXECTL_MAX
2288 };
2289 
2290 union rtw89_btc_fbtc_rxflct {
2291 	u8 val;
2292 	u8 type: 3;
2293 	u8 tgln_n: 5;
2294 };
2295 
2296 enum rtw89_btc_cxst_state {
2297 	CXST_OFF = 0x0,
2298 	CXST_B2W = 0x1,
2299 	CXST_W1 = 0x2,
2300 	CXST_W2 = 0x3,
2301 	CXST_W2B = 0x4,
2302 	CXST_B1 = 0x5,
2303 	CXST_B2 = 0x6,
2304 	CXST_B3 = 0x7,
2305 	CXST_B4 = 0x8,
2306 	CXST_LK = 0x9,
2307 	CXST_BLK = 0xa,
2308 	CXST_E2G = 0xb,
2309 	CXST_E5G = 0xc,
2310 	CXST_EBT = 0xd,
2311 	CXST_ENULL = 0xe,
2312 	CXST_WLK = 0xf,
2313 	CXST_W1FDD = 0x10,
2314 	CXST_B1FDD = 0x11,
2315 	CXST_MAX = 0x12,
2316 };
2317 
2318 enum rtw89_btc_cxevnt {
2319 	CXEVNT_TDMA_ENTRY = 0x0,
2320 	CXEVNT_WL_TMR,
2321 	CXEVNT_B1_TMR,
2322 	CXEVNT_B2_TMR,
2323 	CXEVNT_B3_TMR,
2324 	CXEVNT_B4_TMR,
2325 	CXEVNT_W2B_TMR,
2326 	CXEVNT_B2W_TMR,
2327 	CXEVNT_BCN_EARLY,
2328 	CXEVNT_A2DP_EMPTY,
2329 	CXEVNT_LK_END,
2330 	CXEVNT_RX_ISR,
2331 	CXEVNT_RX_FC0,
2332 	CXEVNT_RX_FC1,
2333 	CXEVNT_BT_RELINK,
2334 	CXEVNT_BT_RETRY,
2335 	CXEVNT_E2G,
2336 	CXEVNT_E5G,
2337 	CXEVNT_EBT,
2338 	CXEVNT_ENULL,
2339 	CXEVNT_DRV_WLK,
2340 	CXEVNT_BCN_OK,
2341 	CXEVNT_BT_CHANGE,
2342 	CXEVNT_EBT_EXTEND,
2343 	CXEVNT_E2G_NULL1,
2344 	CXEVNT_B1FDD_TMR,
2345 	CXEVNT_MAX
2346 };
2347 
2348 enum {
2349 	CXBCN_ALL = 0x0,
2350 	CXBCN_ALL_OK,
2351 	CXBCN_BT_SLOT,
2352 	CXBCN_BT_OK,
2353 	CXBCN_MAX
2354 };
2355 
2356 enum btc_slot_type {
2357 	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2358 	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2359 	CXSTYPE_NUM,
2360 };
2361 
2362 enum { /* TIME */
2363 	CXT_BT = 0x0,
2364 	CXT_WL = 0x1,
2365 	CXT_MAX
2366 };
2367 
2368 enum { /* TIME-A2DP */
2369 	CXT_FLCTRL_OFF = 0x0,
2370 	CXT_FLCTRL_ON = 0x1,
2371 	CXT_FLCTRL_MAX
2372 };
2373 
2374 enum { /* STEP TYPE */
2375 	CXSTEP_NONE = 0x0,
2376 	CXSTEP_EVNT = 0x1,
2377 	CXSTEP_SLOT = 0x2,
2378 	CXSTEP_MAX,
2379 };
2380 
2381 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2382 	RPT_BT_AFH_SEQ_LEGACY = 0x10,
2383 	RPT_BT_AFH_SEQ_LE = 0x20
2384 };
2385 
2386 #define BTC_DBG_MAX1  32
2387 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2388 	u8 fver; /* btc_ver::fcxgpiodbg */
2389 	u8 rsvd;
2390 	__le16 rsvd2;
2391 	__le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2392 	__le32 pre_state; /* the debug signal is 1 or 0  */
2393 	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2394 } __packed;
2395 
2396 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2397 	u8 fver;
2398 	u8 rsvd0;
2399 	u8 rsvd1;
2400 	u8 rsvd2;
2401 
2402 	u8 gpio_map[BTC_DBG_MAX1];
2403 
2404 	__le32 en_map;
2405 	__le32 pre_state;
2406 } __packed;
2407 
2408 union rtw89_btc_fbtc_gpio_dbg {
2409 	struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2410 	struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2411 };
2412 
2413 struct rtw89_btc_fbtc_mreg_val_v1 {
2414 	u8 fver; /* btc_ver::fcxmreg */
2415 	u8 reg_num;
2416 	__le16 rsvd;
2417 	__le32 mreg_val[CXMREG_MAX];
2418 } __packed;
2419 
2420 struct rtw89_btc_fbtc_mreg_val_v2 {
2421 	u8 fver; /* btc_ver::fcxmreg */
2422 	u8 reg_num;
2423 	__le16 rsvd;
2424 	__le32 mreg_val[CXMREG_MAX_V2];
2425 } __packed;
2426 
2427 struct rtw89_btc_fbtc_mreg_val_v7 {
2428 	u8 fver;
2429 	u8 reg_num;
2430 	u8 rsvd0;
2431 	u8 rsvd1;
2432 	__le32 mreg_val[CXMREG_MAX_V2];
2433 } __packed;
2434 
2435 union rtw89_btc_fbtc_mreg_val {
2436 	struct rtw89_btc_fbtc_mreg_val_v1 v1;
2437 	struct rtw89_btc_fbtc_mreg_val_v2 v2;
2438 	struct rtw89_btc_fbtc_mreg_val_v7 v7;
2439 };
2440 
2441 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2442 	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2443 	  .offset = cpu_to_le32(__offset), }
2444 
2445 struct rtw89_btc_fbtc_mreg {
2446 	__le16 type;
2447 	__le16 bytes;
2448 	__le32 offset;
2449 } __packed;
2450 
2451 struct rtw89_btc_fbtc_slot {
2452 	__le16 dur;
2453 	__le32 cxtbl;
2454 	__le16 cxtype;
2455 } __packed;
2456 
2457 struct rtw89_btc_fbtc_slots {
2458 	u8 fver; /* btc_ver::fcxslots */
2459 	u8 tbl_num;
2460 	__le16 rsvd;
2461 	__le32 update_map;
2462 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2463 } __packed;
2464 
2465 struct rtw89_btc_fbtc_slot_v7 {
2466 	__le16 dur; /* slot duration */
2467 	__le16 cxtype;
2468 	__le32 cxtbl;
2469 } __packed;
2470 
2471 struct rtw89_btc_fbtc_slot_u16 {
2472 	__le16 dur; /* slot duration */
2473 	__le16 cxtype;
2474 	__le16 cxtbl_l16; /* coex table [15:0] */
2475 	__le16 cxtbl_h16; /* coex table [31:16] */
2476 } __packed;
2477 
2478 struct rtw89_btc_fbtc_1slot_v7 {
2479 	u8 fver;
2480 	u8 sid; /* slot id */
2481 	__le16 rsvd;
2482 	struct rtw89_btc_fbtc_slot_v7 slot;
2483 } __packed;
2484 
2485 struct rtw89_btc_fbtc_slots_v7 {
2486 	u8 fver;
2487 	u8 slot_cnt;
2488 	u8 rsvd0;
2489 	u8 rsvd1;
2490 	struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2491 	__le32 update_map;
2492 } __packed;
2493 
2494 union rtw89_btc_fbtc_slots_info {
2495 	struct rtw89_btc_fbtc_slots v1;
2496 	struct rtw89_btc_fbtc_slots_v7 v7;
2497 } __packed;
2498 
2499 struct rtw89_btc_fbtc_step {
2500 	u8 type;
2501 	u8 val;
2502 	__le16 difft;
2503 } __packed;
2504 
2505 struct rtw89_btc_fbtc_steps_v2 {
2506 	u8 fver; /* btc_ver::fcxstep */
2507 	u8 rsvd;
2508 	__le16 cnt;
2509 	__le16 pos_old;
2510 	__le16 pos_new;
2511 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2512 } __packed;
2513 
2514 struct rtw89_btc_fbtc_steps_v3 {
2515 	u8 fver;
2516 	u8 en;
2517 	__le16 rsvd;
2518 	__le32 cnt;
2519 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2520 } __packed;
2521 
2522 union rtw89_btc_fbtc_steps_info {
2523 	struct rtw89_btc_fbtc_steps_v2 v2;
2524 	struct rtw89_btc_fbtc_steps_v3 v3;
2525 };
2526 
2527 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2528 	u8 fver; /* btc_ver::fcxcysta */
2529 	u8 rsvd;
2530 	__le16 cycles; /* total cycle number */
2531 	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
2532 	__le16 a2dpept; /* a2dp empty cnt */
2533 	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
2534 	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2535 	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2536 	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2537 	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2538 	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2539 	__le16 tavg_a2dpept; /* avg a2dp empty time */
2540 	__le16 tmax_a2dpept; /* max a2dp empty time */
2541 	__le16 tavg_lk; /* avg leak-slot time */
2542 	__le16 tmax_lk; /* max leak-slot time */
2543 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2544 	__le32 bcn_cnt[CXBCN_MAX];
2545 	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
2546 	__le32 collision_cnt; /* counter for event/timer occur at same time */
2547 	__le32 skip_cnt;
2548 	__le32 exception;
2549 	__le32 except_cnt;
2550 	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2551 } __packed;
2552 
2553 struct rtw89_btc_fbtc_fdd_try_info {
2554 	__le16 cycles[CXT_FLCTRL_MAX];
2555 	__le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2556 	__le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2557 } __packed;
2558 
2559 struct rtw89_btc_fbtc_cycle_time_info {
2560 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2561 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2562 	__le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2563 } __packed;
2564 
2565 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2566 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2567 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2568 } __packed;
2569 
2570 struct rtw89_btc_fbtc_a2dp_trx_stat {
2571 	u8 empty_cnt;
2572 	u8 retry_cnt;
2573 	u8 tx_rate;
2574 	u8 tx_cnt;
2575 	u8 ack_cnt;
2576 	u8 nack_cnt;
2577 	u8 rsvd1;
2578 	u8 rsvd2;
2579 } __packed;
2580 
2581 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2582 	u8 empty_cnt;
2583 	u8 retry_cnt;
2584 	u8 tx_rate;
2585 	u8 tx_cnt;
2586 	u8 ack_cnt;
2587 	u8 nack_cnt;
2588 	u8 no_empty_cnt;
2589 	u8 rsvd;
2590 } __packed;
2591 
2592 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2593 	__le16 cnt; /* a2dp empty cnt */
2594 	__le16 cnt_timeout; /* a2dp empty timeout cnt*/
2595 	__le16 tavg; /* avg a2dp empty time */
2596 	__le16 tmax; /* max a2dp empty time */
2597 } __packed;
2598 
2599 struct rtw89_btc_fbtc_cycle_leak_info {
2600 	__le32 cnt_rximr; /* the rximr occur at leak slot  */
2601 	__le16 tavg; /* avg leak-slot time */
2602 	__le16 tmax; /* max leak-slot time */
2603 } __packed;
2604 
2605 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2606 	__le16 tavg;
2607 	__le16 tamx;
2608 	__le32 cnt_rximr;
2609 } __packed;
2610 
2611 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2612 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2613 
2614 struct rtw89_btc_fbtc_cycle_fddt_info {
2615 	__le16 train_cycle;
2616 	__le16 tp;
2617 
2618 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2619 	s8 bt_tx_power; /* decrease Tx power (dB) */
2620 	s8 bt_rx_gain;  /* LNA constrain level */
2621 	u8 no_empty_cnt;
2622 
2623 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2624 	u8 cn; /* condition_num */
2625 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2626 	u8 train_result; /* refer to enum btc_fddt_check_map */
2627 } __packed;
2628 
2629 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2630 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2631 
2632 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2633 	__le16 train_cycle;
2634 	__le16 tp;
2635 
2636 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2637 	s8 bt_tx_power; /* decrease Tx power (dB) */
2638 	s8 bt_rx_gain;  /* LNA constrain level */
2639 	u8 no_empty_cnt;
2640 
2641 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2642 	u8 cn; /* condition_num */
2643 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2644 	u8 train_result; /* refer to enum btc_fddt_check_map */
2645 } __packed;
2646 
2647 struct rtw89_btc_fbtc_fddt_cell_status {
2648 	s8 wl_tx_pwr;
2649 	s8 bt_tx_pwr;
2650 	s8 bt_rx_gain;
2651 	u8 state_phase; /* [0:3] train state, [4:7] train phase */
2652 } __packed;
2653 
2654 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2655 	u8 fver;
2656 	u8 rsvd;
2657 	__le16 cycles; /* total cycle number */
2658 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2659 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2660 	struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2661 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2662 	struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2663 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2664 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2665 	__le32 bcn_cnt[CXBCN_MAX];
2666 	__le32 collision_cnt; /* counter for event/timer occur at the same time */
2667 	__le32 skip_cnt;
2668 	__le32 except_cnt;
2669 	__le32 except_map;
2670 } __packed;
2671 
2672 #define FDD_TRAIN_WL_DIRECTION 2
2673 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2674 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2675 
2676 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2677 	u8 fver;
2678 	u8 rsvd;
2679 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2680 	u8 except_cnt;
2681 
2682 	__le16 skip_cnt;
2683 	__le16 cycles; /* total cycle number */
2684 
2685 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2686 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2687 	__le16 bcn_cnt[CXBCN_MAX];
2688 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2689 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2690 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2691 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2692 	struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2693 	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2694 							 [FDD_TRAIN_WL_RSSI_LEVEL]
2695 							 [FDD_TRAIN_BT_RSSI_LEVEL];
2696 	__le32 except_map;
2697 } __packed;
2698 
2699 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2700 	u8 fver;
2701 	u8 rsvd;
2702 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2703 	u8 except_cnt;
2704 	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2705 
2706 	__le16 skip_cnt;
2707 	__le16 cycles; /* total cycle number */
2708 
2709 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2710 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2711 	__le16 bcn_cnt[CXBCN_MAX];
2712 	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2713 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2714 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2715 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2716 	struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2717 	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2718 							 [FDD_TRAIN_WL_RSSI_LEVEL]
2719 							 [FDD_TRAIN_BT_RSSI_LEVEL];
2720 	__le32 except_map;
2721 } __packed;
2722 
2723 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2724 	u8 fver;
2725 	u8 rsvd;
2726 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2727 	u8 except_cnt;
2728 
2729 	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2730 
2731 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2732 
2733 	__le16 skip_cnt;
2734 	__le16 cycles; /* total cycle number */
2735 
2736 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2737 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2738 	__le16 bcn_cnt[CXBCN_MAX];
2739 
2740 	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2741 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2742 	struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2743 
2744 	__le32 except_map;
2745 } __packed;
2746 
2747 union rtw89_btc_fbtc_cysta_info {
2748 	struct rtw89_btc_fbtc_cysta_v2 v2;
2749 	struct rtw89_btc_fbtc_cysta_v3 v3;
2750 	struct rtw89_btc_fbtc_cysta_v4 v4;
2751 	struct rtw89_btc_fbtc_cysta_v5 v5;
2752 	struct rtw89_btc_fbtc_cysta_v7 v7;
2753 };
2754 
2755 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2756 	u8 fver; /* btc_ver::fcxnullsta */
2757 	u8 rsvd;
2758 	__le16 rsvd2;
2759 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2760 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2761 	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2762 } __packed;
2763 
2764 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2765 	u8 fver; /* btc_ver::fcxnullsta */
2766 	u8 rsvd;
2767 	__le16 rsvd2;
2768 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2769 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2770 	__le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2771 } __packed;
2772 
2773 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2774 	u8 fver;
2775 	u8 rsvd0;
2776 	u8 rsvd1;
2777 	u8 rsvd2;
2778 
2779 	__le32 tmax[2];
2780 	__le32 tavg[2];
2781 	__le32 result[2][5];
2782 } __packed;
2783 
2784 union rtw89_btc_fbtc_cynullsta_info {
2785 	struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2786 	struct rtw89_btc_fbtc_cynullsta_v2 v2;
2787 	struct rtw89_btc_fbtc_cynullsta_v7 v7;
2788 };
2789 
2790 struct rtw89_btc_fbtc_btver_v1 {
2791 	u8 fver; /* btc_ver::fcxbtver */
2792 	u8 rsvd;
2793 	__le16 rsvd2;
2794 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2795 	__le32 fw_ver;
2796 	__le32 feature;
2797 } __packed;
2798 
2799 struct rtw89_btc_fbtc_btver_v7 {
2800 	u8 fver;
2801 	u8 rsvd0;
2802 	u8 rsvd1;
2803 	u8 rsvd2;
2804 
2805 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2806 	__le32 fw_ver;
2807 	__le32 feature;
2808 } __packed;
2809 
2810 union rtw89_btc_fbtc_btver {
2811 	struct rtw89_btc_fbtc_btver_v1 v1;
2812 	struct rtw89_btc_fbtc_btver_v7 v7;
2813 } __packed;
2814 
2815 struct rtw89_btc_fbtc_btafh {
2816 	u8 fver; /* btc_ver::fcxbtafh */
2817 	u8 rsvd;
2818 	__le16 rsvd2;
2819 	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2820 	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2821 	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2822 } __packed;
2823 
2824 struct rtw89_btc_fbtc_btafh_v2 {
2825 	u8 fver; /* btc_ver::fcxbtafh */
2826 	u8 rsvd;
2827 	u8 rsvd2;
2828 	u8 map_type;
2829 	u8 afh_l[4];
2830 	u8 afh_m[4];
2831 	u8 afh_h[4];
2832 	u8 afh_le_a[4];
2833 	u8 afh_le_b[4];
2834 } __packed;
2835 
2836 struct rtw89_btc_fbtc_btafh_v7 {
2837 	u8 fver;
2838 	u8 map_type;
2839 	u8 rsvd0;
2840 	u8 rsvd1;
2841 	u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2842 	u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2843 	u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2844 	u8 afh_le_a[4];
2845 	u8 afh_le_b[4];
2846 } __packed;
2847 
2848 struct rtw89_btc_fbtc_btdevinfo {
2849 	u8 fver; /* btc_ver::fcxbtdevinfo */
2850 	u8 rsvd;
2851 	__le16 vendor_id;
2852 	__le32 dev_name; /* only 24 bits valid */
2853 	__le32 flush_time;
2854 } __packed;
2855 
2856 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2857 struct rtw89_btc_rf_trx_para {
2858 	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2859 	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
2860 	u8 bt_tx_power; /* decrease Tx power (dB) */
2861 	u8 bt_rx_gain;  /* LNA constrain level */
2862 };
2863 
2864 struct rtw89_btc_trx_info {
2865 	u8 tx_lvl;
2866 	u8 rx_lvl;
2867 	u8 wl_rssi;
2868 	u8 bt_rssi;
2869 
2870 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2871 	s8 rx_gain;  /* rx gain table index (TBD.) */
2872 	s8 bt_tx_power; /* decrease Tx power (dB) */
2873 	s8 bt_rx_gain;  /* LNA constrain level */
2874 
2875 	u8 cn; /* condition_num */
2876 	s8 nhm;
2877 	u8 bt_profile;
2878 	u8 rsvd2;
2879 
2880 	u16 tx_rate;
2881 	u16 rx_rate;
2882 
2883 	u32 tx_tp;
2884 	u32 rx_tp;
2885 	u32 rx_err_ratio;
2886 };
2887 
2888 union rtw89_btc_fbtc_slot_u {
2889 	struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2890 	struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2891 };
2892 
2893 struct rtw89_btc_dm {
2894 	union rtw89_btc_fbtc_slot_u slot;
2895 	union rtw89_btc_fbtc_slot_u slot_now;
2896 	struct rtw89_btc_fbtc_tdma tdma;
2897 	struct rtw89_btc_fbtc_tdma tdma_now;
2898 	struct rtw89_mac_ax_coex_gnt gnt;
2899 	union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2900 	struct rtw89_btc_rf_trx_para rf_trx_para;
2901 	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2902 	struct rtw89_btc_dm_step dm_step;
2903 	struct rtw89_btc_wl_scc_ctrl wl_scc;
2904 	struct rtw89_btc_trx_info trx_info;
2905 	union rtw89_btc_dm_error_map error;
2906 	u32 cnt_dm[BTC_DCNT_NUM];
2907 	u32 cnt_notify[BTC_NCNT_NUM];
2908 
2909 	u32 update_slot_map;
2910 	u32 set_ant_path;
2911 	u32 e2g_slot_limit;
2912 	u32 e2g_slot_nulltx_time;
2913 
2914 	u32 wl_only: 1;
2915 	u32 wl_fw_cx_offload: 1;
2916 	u32 freerun: 1;
2917 	u32 fddt_train: 1;
2918 	u32 wl_ps_ctrl: 2;
2919 	u32 wl_mimo_ps: 1;
2920 	u32 leak_ap: 1;
2921 	u32 noisy_level: 3;
2922 	u32 coex_info_map: 8;
2923 	u32 bt_only: 1;
2924 	u32 wl_btg_rx: 2;
2925 	u32 trx_para_level: 8;
2926 	u32 wl_stb_chg: 1;
2927 	u32 pta_owner: 1;
2928 
2929 	u32 tdma_instant_excute: 1;
2930 	u32 wl_btg_rx_rb: 2;
2931 
2932 	u16 slot_dur[CXST_MAX];
2933 	u16 bt_slot_flood;
2934 
2935 	u8 run_reason;
2936 	u8 run_action;
2937 
2938 	u8 wl_pre_agc: 2;
2939 	u8 wl_lna2: 1;
2940 	u8 wl_pre_agc_rb: 2;
2941 	u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2942 	u8 slot_req_more: 1;
2943 };
2944 
2945 struct rtw89_btc_ctrl {
2946 	u32 manual: 1;
2947 	u32 igno_bt: 1;
2948 	u32 always_freerun: 1;
2949 	u32 trace_step: 16;
2950 	u32 rsvd: 12;
2951 };
2952 
2953 struct rtw89_btc_ctrl_v7 {
2954 	u8 manual;
2955 	u8 igno_bt;
2956 	u8 always_freerun;
2957 	u8 rsvd;
2958 } __packed;
2959 
2960 union rtw89_btc_ctrl_list {
2961 	struct rtw89_btc_ctrl ctrl;
2962 	struct rtw89_btc_ctrl_v7 ctrl_v7;
2963 };
2964 
2965 struct rtw89_btc_dbg {
2966 	/* cmd "rb" */
2967 	bool rb_done;
2968 	u32 rb_val;
2969 };
2970 
2971 enum rtw89_btc_btf_fw_event {
2972 	BTF_EVNT_RPT = 0,
2973 	BTF_EVNT_BT_INFO = 1,
2974 	BTF_EVNT_BT_SCBD = 2,
2975 	BTF_EVNT_BT_REG = 3,
2976 	BTF_EVNT_CX_RUNINFO = 4,
2977 	BTF_EVNT_BT_PSD = 5,
2978 	BTF_EVNT_BUF_OVERFLOW,
2979 	BTF_EVNT_C2H_LOOPBACK,
2980 	BTF_EVNT_MAX,
2981 };
2982 
2983 enum btf_fw_event_report {
2984 	BTC_RPT_TYPE_CTRL = 0x0,
2985 	BTC_RPT_TYPE_TDMA,
2986 	BTC_RPT_TYPE_SLOT,
2987 	BTC_RPT_TYPE_CYSTA,
2988 	BTC_RPT_TYPE_STEP,
2989 	BTC_RPT_TYPE_NULLSTA,
2990 	BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
2991 	BTC_RPT_TYPE_MREG,
2992 	BTC_RPT_TYPE_GPIO_DBG,
2993 	BTC_RPT_TYPE_BT_VER,
2994 	BTC_RPT_TYPE_BT_SCAN,
2995 	BTC_RPT_TYPE_BT_AFH,
2996 	BTC_RPT_TYPE_BT_DEVICE,
2997 	BTC_RPT_TYPE_TEST,
2998 	BTC_RPT_TYPE_MAX = 31,
2999 
3000 	__BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3001 	__BTC_RPT_TYPE_V0_MAX = 12,
3002 };
3003 
3004 enum rtw_btc_btf_reg_type {
3005 	REG_MAC = 0x0,
3006 	REG_BB = 0x1,
3007 	REG_RF = 0x2,
3008 	REG_BT_RF = 0x3,
3009 	REG_BT_MODEM = 0x4,
3010 	REG_BT_BLUEWIZE = 0x5,
3011 	REG_BT_VENDOR = 0x6,
3012 	REG_BT_LE = 0x7,
3013 	REG_MAX_TYPE,
3014 };
3015 
3016 struct rtw89_btc_rpt_cmn_info {
3017 	u32 rx_cnt;
3018 	u32 rx_len;
3019 	u32 req_len; /* expected rsp len */
3020 	u8 req_fver; /* expected rsp fver */
3021 	u8 rsp_fver; /* fver from fw */
3022 	u8 valid;
3023 } __packed;
3024 
3025 union rtw89_btc_fbtc_btafh_info {
3026 	struct rtw89_btc_fbtc_btafh v1;
3027 	struct rtw89_btc_fbtc_btafh_v2 v2;
3028 };
3029 
3030 struct rtw89_btc_report_ctrl_state {
3031 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3032 	union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3033 };
3034 
3035 struct rtw89_btc_rpt_fbtc_tdma {
3036 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3037 	union rtw89_btc_fbtc_tdma_le32 finfo;
3038 };
3039 
3040 struct rtw89_btc_rpt_fbtc_slots {
3041 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3042 	union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3043 };
3044 
3045 struct rtw89_btc_rpt_fbtc_cysta {
3046 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3047 	union rtw89_btc_fbtc_cysta_info finfo;
3048 };
3049 
3050 struct rtw89_btc_rpt_fbtc_step {
3051 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3052 	union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3053 };
3054 
3055 struct rtw89_btc_rpt_fbtc_nullsta {
3056 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3057 	union rtw89_btc_fbtc_cynullsta_info finfo;
3058 };
3059 
3060 struct rtw89_btc_rpt_fbtc_mreg {
3061 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3062 	union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3063 };
3064 
3065 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3066 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3067 	union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3068 };
3069 
3070 struct rtw89_btc_rpt_fbtc_btver {
3071 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3072 	union rtw89_btc_fbtc_btver finfo; /* info from fw */
3073 };
3074 
3075 struct rtw89_btc_rpt_fbtc_btscan {
3076 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3077 	union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3078 };
3079 
3080 struct rtw89_btc_rpt_fbtc_btafh {
3081 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3082 	union rtw89_btc_fbtc_btafh_info finfo;
3083 };
3084 
3085 struct rtw89_btc_rpt_fbtc_btdev {
3086 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3087 	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3088 };
3089 
3090 enum rtw89_btc_btfre_type {
3091 	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3092 	BTFRE_UNDEF_TYPE,
3093 	BTFRE_EXCEPTION,
3094 	BTFRE_MAX,
3095 };
3096 
3097 struct rtw89_btc_btf_fwinfo {
3098 	u32 cnt_c2h;
3099 	u32 cnt_h2c;
3100 	u32 cnt_h2c_fail;
3101 	u32 event[BTF_EVNT_MAX];
3102 
3103 	u32 err[BTFRE_MAX];
3104 	u32 len_mismch;
3105 	u32 fver_mismch;
3106 	u32 rpt_en_map;
3107 
3108 	struct rtw89_btc_report_ctrl_state rpt_ctrl;
3109 	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3110 	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3111 	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3112 	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3113 	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3114 	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3115 	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3116 	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3117 	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3118 	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3119 	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3120 };
3121 
3122 struct rtw89_btc_ver {
3123 	enum rtw89_core_chip_id chip_id;
3124 	u32 fw_ver_code;
3125 
3126 	u8 fcxbtcrpt;
3127 	u8 fcxtdma;
3128 	u8 fcxslots;
3129 	u8 fcxcysta;
3130 	u8 fcxstep;
3131 	u8 fcxnullsta;
3132 	u8 fcxmreg;
3133 	u8 fcxgpiodbg;
3134 	u8 fcxbtver;
3135 	u8 fcxbtscan;
3136 	u8 fcxbtafh;
3137 	u8 fcxbtdevinfo;
3138 	u8 fwlrole;
3139 	u8 frptmap;
3140 	u8 fcxctrl;
3141 	u8 fcxinit;
3142 
3143 	u8 fwevntrptl;
3144 	u8 drvinfo_type;
3145 	u16 info_buf;
3146 	u8 max_role_num;
3147 };
3148 
3149 #define RTW89_BTC_POLICY_MAXLEN 512
3150 
3151 struct rtw89_btc {
3152 	const struct rtw89_btc_ver *ver;
3153 
3154 	struct rtw89_btc_cx cx;
3155 	struct rtw89_btc_dm dm;
3156 	union rtw89_btc_ctrl_list ctrl;
3157 	union rtw89_btc_module_info mdinfo;
3158 	struct rtw89_btc_btf_fwinfo fwinfo;
3159 	struct rtw89_btc_dbg dbg;
3160 
3161 	struct work_struct eapol_notify_work;
3162 	struct work_struct arp_notify_work;
3163 	struct work_struct dhcp_notify_work;
3164 	struct work_struct icmp_notify_work;
3165 
3166 	u32 bt_req_len;
3167 
3168 	u8 policy[RTW89_BTC_POLICY_MAXLEN];
3169 	u8 ant_type;
3170 	u8 btg_pos;
3171 	u16 policy_len;
3172 	u16 policy_type;
3173 	u32 hubmsg_cnt;
3174 	bool bt_req_en;
3175 	bool update_policy_force;
3176 	bool lps;
3177 	bool manual_ctrl;
3178 };
3179 
3180 enum rtw89_btc_hmsg {
3181 	RTW89_BTC_HMSG_TMR_EN = 0x0,
3182 	RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3183 	RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3184 	RTW89_BTC_HMSG_FW_EV = 0x3,
3185 	RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3186 	RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3187 
3188 	NUM_OF_RTW89_BTC_HMSG,
3189 };
3190 
3191 enum rtw89_ra_mode {
3192 	RTW89_RA_MODE_CCK = BIT(0),
3193 	RTW89_RA_MODE_OFDM = BIT(1),
3194 	RTW89_RA_MODE_HT = BIT(2),
3195 	RTW89_RA_MODE_VHT = BIT(3),
3196 	RTW89_RA_MODE_HE = BIT(4),
3197 	RTW89_RA_MODE_EHT = BIT(5),
3198 };
3199 
3200 enum rtw89_ra_report_mode {
3201 	RTW89_RA_RPT_MODE_LEGACY,
3202 	RTW89_RA_RPT_MODE_HT,
3203 	RTW89_RA_RPT_MODE_VHT,
3204 	RTW89_RA_RPT_MODE_HE,
3205 	RTW89_RA_RPT_MODE_EHT,
3206 };
3207 
3208 enum rtw89_dig_noisy_level {
3209 	RTW89_DIG_NOISY_LEVEL0 = -1,
3210 	RTW89_DIG_NOISY_LEVEL1 = 0,
3211 	RTW89_DIG_NOISY_LEVEL2 = 1,
3212 	RTW89_DIG_NOISY_LEVEL3 = 2,
3213 	RTW89_DIG_NOISY_LEVEL_MAX = 3,
3214 };
3215 
3216 enum rtw89_gi_ltf {
3217 	RTW89_GILTF_LGI_4XHE32 = 0,
3218 	RTW89_GILTF_SGI_4XHE08 = 1,
3219 	RTW89_GILTF_2XHE16 = 2,
3220 	RTW89_GILTF_2XHE08 = 3,
3221 	RTW89_GILTF_1XHE16 = 4,
3222 	RTW89_GILTF_1XHE08 = 5,
3223 	RTW89_GILTF_MAX
3224 };
3225 
3226 enum rtw89_rx_frame_type {
3227 	RTW89_RX_TYPE_MGNT = 0,
3228 	RTW89_RX_TYPE_CTRL = 1,
3229 	RTW89_RX_TYPE_DATA = 2,
3230 	RTW89_RX_TYPE_RSVD = 3,
3231 };
3232 
3233 enum rtw89_efuse_block {
3234 	RTW89_EFUSE_BLOCK_SYS = 0,
3235 	RTW89_EFUSE_BLOCK_RF = 1,
3236 	RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3237 	RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3238 	RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3239 	RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3240 	RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3241 	RTW89_EFUSE_BLOCK_ADIE = 7,
3242 
3243 	RTW89_EFUSE_BLOCK_NUM,
3244 	RTW89_EFUSE_BLOCK_IGNORE,
3245 };
3246 
3247 struct rtw89_ra_info {
3248 	u8 is_dis_ra:1;
3249 	/* Bit0 : CCK
3250 	 * Bit1 : OFDM
3251 	 * Bit2 : HT
3252 	 * Bit3 : VHT
3253 	 * Bit4 : HE
3254 	 * Bit5 : EHT
3255 	 */
3256 	u8 mode_ctrl:6;
3257 	u8 bw_cap:3; /* enum rtw89_bandwidth */
3258 	u8 macid;
3259 	u8 dcm_cap:1;
3260 	u8 er_cap:1;
3261 	u8 init_rate_lv:2;
3262 	u8 upd_all:1;
3263 	u8 en_sgi:1;
3264 	u8 ldpc_cap:1;
3265 	u8 stbc_cap:1;
3266 	u8 ss_num:3;
3267 	u8 giltf:3;
3268 	u8 upd_bw_nss_mask:1;
3269 	u8 upd_mask:1;
3270 	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3271 	/* BFee CSI */
3272 	u8 band_num;
3273 	u8 ra_csi_rate_en:1;
3274 	u8 fixed_csi_rate_en:1;
3275 	u8 cr_tbl_sel:1;
3276 	u8 fix_giltf_en:1;
3277 	u8 fix_giltf:3;
3278 	u8 rsvd2:1;
3279 	u8 csi_mcs_ss_idx;
3280 	u8 csi_mode:2;
3281 	u8 csi_gi_ltf:3;
3282 	u8 csi_bw:3;
3283 };
3284 
3285 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3286 #define RTW89_PPDU_MAC_INFO_SIZE 8
3287 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3288 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3289 
3290 #define RTW89_MAX_RX_AGG_NUM 64
3291 #define RTW89_MAX_TX_AGG_NUM 128
3292 
3293 struct rtw89_ampdu_params {
3294 	u16 agg_num;
3295 	bool amsdu;
3296 };
3297 
3298 struct rtw89_ra_report {
3299 	struct rate_info txrate;
3300 	u32 bit_rate;
3301 	u16 hw_rate;
3302 	bool might_fallback_legacy;
3303 };
3304 
3305 DECLARE_EWMA(rssi, 10, 16);
3306 DECLARE_EWMA(evm, 10, 16);
3307 DECLARE_EWMA(snr, 10, 16);
3308 
3309 struct rtw89_ba_cam_entry {
3310 	struct list_head list;
3311 	u8 tid;
3312 };
3313 
3314 #define RTW89_MAX_ADDR_CAM_NUM		128
3315 #define RTW89_MAX_BSSID_CAM_NUM		20
3316 #define RTW89_MAX_SEC_CAM_NUM		128
3317 #define RTW89_MAX_BA_CAM_NUM		24
3318 #define RTW89_SEC_CAM_IN_ADDR_CAM	7
3319 
3320 struct rtw89_addr_cam_entry {
3321 	u8 addr_cam_idx;
3322 	u8 offset;
3323 	u8 len;
3324 	u8 valid	: 1;
3325 	u8 addr_mask	: 6;
3326 	u8 wapi		: 1;
3327 	u8 mask_sel	: 2;
3328 	u8 bssid_cam_idx: 6;
3329 
3330 	u8 sec_ent_mode;
3331 	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3332 	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3333 	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3334 };
3335 
3336 struct rtw89_bssid_cam_entry {
3337 	u8 bssid[ETH_ALEN];
3338 	u8 phy_idx;
3339 	u8 bssid_cam_idx;
3340 	u8 offset;
3341 	u8 len;
3342 	u8 valid : 1;
3343 	u8 num;
3344 };
3345 
3346 struct rtw89_sec_cam_entry {
3347 	u8 sec_cam_idx;
3348 	u8 offset;
3349 	u8 len;
3350 	u8 type : 4;
3351 	u8 ext_key : 1;
3352 	u8 spp_mode : 1;
3353 	/* 256 bits */
3354 	u8 key[32];
3355 };
3356 
3357 struct rtw89_sta {
3358 	u8 mac_id;
3359 	bool disassoc;
3360 	bool er_cap;
3361 	struct rtw89_dev *rtwdev;
3362 	struct rtw89_vif *rtwvif;
3363 	struct rtw89_ra_info ra;
3364 	struct rtw89_ra_report ra_report;
3365 	int max_agg_wait;
3366 	u8 prev_rssi;
3367 	struct ewma_rssi avg_rssi;
3368 	struct ewma_rssi rssi[RF_PATH_MAX];
3369 	struct ewma_snr avg_snr;
3370 	struct ewma_evm evm_1ss;
3371 	struct ewma_evm evm_min[RF_PATH_MAX];
3372 	struct ewma_evm evm_max[RF_PATH_MAX];
3373 	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
3374 	DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
3375 	struct ieee80211_rx_status rx_status;
3376 	u16 rx_hw_rate;
3377 	__le32 htc_template;
3378 	struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3379 	struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3380 	struct list_head ba_cam_list;
3381 	struct sk_buff_head roc_queue;
3382 
3383 	bool use_cfg_mask;
3384 	struct cfg80211_bitrate_mask mask;
3385 
3386 	bool cctl_tx_time;
3387 	u32 ampdu_max_time:4;
3388 	bool cctl_tx_retry_limit;
3389 	u32 data_tx_cnt_lmt:6;
3390 };
3391 
3392 struct rtw89_efuse {
3393 	bool valid;
3394 	bool power_k_valid;
3395 	u8 xtal_cap;
3396 	u8 addr[ETH_ALEN];
3397 	u8 rfe_type;
3398 	char country_code[2];
3399 };
3400 
3401 struct rtw89_phy_rate_pattern {
3402 	u64 ra_mask;
3403 	u16 rate;
3404 	u8 ra_mode;
3405 	bool enable;
3406 };
3407 
3408 struct rtw89_tx_wait_info {
3409 	struct rcu_head rcu_head;
3410 	struct completion completion;
3411 	bool tx_done;
3412 };
3413 
3414 struct rtw89_tx_skb_data {
3415 	struct rtw89_tx_wait_info __rcu *wait;
3416 	u8 hci_priv[];
3417 };
3418 
3419 #define RTW89_ROC_IDLE_TIMEOUT 500
3420 #define RTW89_ROC_TX_TIMEOUT 30
3421 enum rtw89_roc_state {
3422 	RTW89_ROC_IDLE,
3423 	RTW89_ROC_NORMAL,
3424 	RTW89_ROC_MGMT,
3425 };
3426 
3427 struct rtw89_roc {
3428 	struct ieee80211_channel chan;
3429 	struct delayed_work roc_work;
3430 	enum ieee80211_roc_type type;
3431 	enum rtw89_roc_state state;
3432 	int duration;
3433 };
3434 
3435 #define RTW89_P2P_MAX_NOA_NUM 2
3436 
3437 struct rtw89_p2p_ie_head {
3438 	u8 eid;
3439 	u8 ie_len;
3440 	u8 oui[3];
3441 	u8 oui_type;
3442 } __packed;
3443 
3444 struct rtw89_noa_attr_head {
3445 	u8 attr_type;
3446 	__le16 attr_len;
3447 	u8 index;
3448 	u8 oppps_ctwindow;
3449 } __packed;
3450 
3451 struct rtw89_p2p_noa_ie {
3452 	struct rtw89_p2p_ie_head p2p_head;
3453 	struct rtw89_noa_attr_head noa_head;
3454 	struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3455 } __packed;
3456 
3457 struct rtw89_p2p_noa_setter {
3458 	struct rtw89_p2p_noa_ie ie;
3459 	u8 noa_count;
3460 	u8 noa_index;
3461 };
3462 
3463 struct rtw89_vif {
3464 	struct list_head list;
3465 	struct rtw89_dev *rtwdev;
3466 	struct rtw89_roc roc;
3467 	bool chanctx_assigned; /* only valid when running with chanctx_ops */
3468 	enum rtw89_chanctx_idx chanctx_idx;
3469 	enum rtw89_reg_6ghz_power reg_6ghz_power;
3470 	struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3471 
3472 	u8 mac_id;
3473 	u8 port;
3474 	u8 mac_addr[ETH_ALEN];
3475 	u8 bssid[ETH_ALEN];
3476 	__be32 ip_addr;
3477 	u8 phy_idx;
3478 	u8 mac_idx;
3479 	u8 net_type;
3480 	u8 wifi_role;
3481 	u8 self_role;
3482 	u8 wmm;
3483 	u8 bcn_hit_cond;
3484 	u8 hit_rule;
3485 	u8 last_noa_nr;
3486 	u64 sync_bcn_tsf;
3487 	bool offchan;
3488 	bool trigger;
3489 	bool lsig_txop;
3490 	u8 tgt_ind;
3491 	u8 frm_tgt_ind;
3492 	bool wowlan_pattern;
3493 	bool wowlan_uc;
3494 	bool wowlan_magic;
3495 	bool is_hesta;
3496 	bool last_a_ctrl;
3497 	bool dyn_tb_bedge_en;
3498 	bool pre_pwr_diff_en;
3499 	bool pwr_diff_en;
3500 	u8 def_tri_idx;
3501 	u32 tdls_peer;
3502 	struct work_struct update_beacon_work;
3503 	struct rtw89_addr_cam_entry addr_cam;
3504 	struct rtw89_bssid_cam_entry bssid_cam;
3505 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3506 	struct rtw89_traffic_stats stats;
3507 	struct rtw89_phy_rate_pattern rate_pattern;
3508 	struct cfg80211_scan_request *scan_req;
3509 	struct ieee80211_scan_ies *scan_ies;
3510 	struct list_head general_pkt_list;
3511 	struct rtw89_p2p_noa_setter p2p_noa;
3512 };
3513 
3514 enum rtw89_lv1_rcvy_step {
3515 	RTW89_LV1_RCVY_STEP_1,
3516 	RTW89_LV1_RCVY_STEP_2,
3517 };
3518 
3519 struct rtw89_hci_ops {
3520 	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3521 	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3522 	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3523 	void (*reset)(struct rtw89_dev *rtwdev);
3524 	int (*start)(struct rtw89_dev *rtwdev);
3525 	void (*stop)(struct rtw89_dev *rtwdev);
3526 	void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3527 	void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3528 	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3529 
3530 	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3531 	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3532 	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3533 	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3534 	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3535 	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3536 
3537 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3538 	int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3539 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
3540 	int (*deinit)(struct rtw89_dev *rtwdev);
3541 
3542 	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3543 	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3544 	void (*dump_err_status)(struct rtw89_dev *rtwdev);
3545 	int (*napi_poll)(struct napi_struct *napi, int budget);
3546 
3547 	/* Deal with locks inside recovery_start and recovery_complete callbacks
3548 	 * by hci instance, and handle things which need to consider under SER.
3549 	 * e.g. turn on/off interrupts except for the one for halt notification.
3550 	 */
3551 	void (*recovery_start)(struct rtw89_dev *rtwdev);
3552 	void (*recovery_complete)(struct rtw89_dev *rtwdev);
3553 
3554 	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3555 	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3556 	void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3557 	int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3558 	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3559 	void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3560 	void (*disable_intr)(struct rtw89_dev *rtwdev);
3561 	void (*enable_intr)(struct rtw89_dev *rtwdev);
3562 	int (*rst_bdram)(struct rtw89_dev *rtwdev);
3563 };
3564 
3565 struct rtw89_hci_info {
3566 	const struct rtw89_hci_ops *ops;
3567 	enum rtw89_hci_type type;
3568 	u32 rpwm_addr;
3569 	u32 cpwm_addr;
3570 	bool paused;
3571 };
3572 
3573 struct rtw89_chip_ops {
3574 	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3575 	int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3576 	void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3577 	void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3578 	void (*bb_reset)(struct rtw89_dev *rtwdev,
3579 			 enum rtw89_phy_idx phy_idx);
3580 	void (*bb_sethw)(struct rtw89_dev *rtwdev);
3581 	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3582 		       u32 addr, u32 mask);
3583 	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3584 			 u32 addr, u32 mask, u32 data);
3585 	void (*set_channel)(struct rtw89_dev *rtwdev,
3586 			    const struct rtw89_chan *chan,
3587 			    enum rtw89_mac_idx mac_idx,
3588 			    enum rtw89_phy_idx phy_idx);
3589 	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3590 				 struct rtw89_channel_help_params *p,
3591 				 const struct rtw89_chan *chan,
3592 				 enum rtw89_mac_idx mac_idx,
3593 				 enum rtw89_phy_idx phy_idx);
3594 	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3595 			  enum rtw89_efuse_block block);
3596 	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3597 	void (*fem_setup)(struct rtw89_dev *rtwdev);
3598 	void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3599 	void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3600 	void (*rfk_init)(struct rtw89_dev *rtwdev);
3601 	void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3602 	void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
3603 	void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3604 				 enum rtw89_phy_idx phy_idx,
3605 				 const struct rtw89_chan *chan);
3606 	void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3607 			 bool start);
3608 	void (*rfk_track)(struct rtw89_dev *rtwdev);
3609 	void (*power_trim)(struct rtw89_dev *rtwdev);
3610 	void (*set_txpwr)(struct rtw89_dev *rtwdev,
3611 			  const struct rtw89_chan *chan,
3612 			  enum rtw89_phy_idx phy_idx);
3613 	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3614 			       enum rtw89_phy_idx phy_idx);
3615 	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3616 	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3617 	void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3618 			       enum rtw89_phy_idx phy_idx);
3619 	void (*query_ppdu)(struct rtw89_dev *rtwdev,
3620 			   struct rtw89_rx_phy_ppdu *phy_ppdu,
3621 			   struct ieee80211_rx_status *status);
3622 	void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3623 				    struct rtw89_rx_phy_ppdu *phy_ppdu);
3624 	void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3625 				enum rtw89_phy_idx phy_idx);
3626 	void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3627 	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3628 				       s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3629 	void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3630 				 enum rtw89_phy_idx phy_idx);
3631 	int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3632 	int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3633 	void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3634 			     struct rtw89_rx_desc_info *desc_info,
3635 			     u8 *data, u32 data_offset);
3636 	void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3637 			    struct rtw89_tx_desc_info *desc_info,
3638 			    void *txdesc);
3639 	void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3640 				  struct rtw89_tx_desc_info *desc_info,
3641 				  void *txdesc);
3642 	int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3643 	int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3644 			   const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3645 	int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3646 			   u32 *tx_en, enum rtw89_sch_tx_sel sel);
3647 	int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3648 	int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3649 				struct rtw89_vif *rtwvif,
3650 				struct rtw89_sta *rtwsta);
3651 	int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3652 				    struct rtw89_vif *rtwvif,
3653 				    struct rtw89_sta *rtwsta);
3654 	int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3655 				  struct ieee80211_vif *vif,
3656 				  struct ieee80211_sta *sta);
3657 	int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3658 				  struct ieee80211_vif *vif,
3659 				  struct ieee80211_sta *sta);
3660 	int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3661 				    struct rtw89_vif *rtwvif,
3662 				    struct rtw89_sta *rtwsta);
3663 	int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3664 				 struct rtw89_vif *rtwvif);
3665 	int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3666 			  bool valid, struct ieee80211_ampdu_params *params);
3667 
3668 	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3669 	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3670 	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3671 	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3672 	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3673 	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3674 	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3675 	void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3676 	void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3677 };
3678 
3679 enum rtw89_dma_ch {
3680 	RTW89_DMA_ACH0 = 0,
3681 	RTW89_DMA_ACH1 = 1,
3682 	RTW89_DMA_ACH2 = 2,
3683 	RTW89_DMA_ACH3 = 3,
3684 	RTW89_DMA_ACH4 = 4,
3685 	RTW89_DMA_ACH5 = 5,
3686 	RTW89_DMA_ACH6 = 6,
3687 	RTW89_DMA_ACH7 = 7,
3688 	RTW89_DMA_B0MG = 8,
3689 	RTW89_DMA_B0HI = 9,
3690 	RTW89_DMA_B1MG = 10,
3691 	RTW89_DMA_B1HI = 11,
3692 	RTW89_DMA_H2C = 12,
3693 	RTW89_DMA_CH_NUM = 13
3694 };
3695 
3696 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3697 
3698 enum rtw89_mlo_dbcc_mode {
3699 	MLO_DBCC_NOT_SUPPORT = 1,
3700 	MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3701 	MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3702 	MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3703 	MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3704 	MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3705 	MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3706 	MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3707 	DBCC_LEGACY = 0xffffffff,
3708 };
3709 
3710 enum rtw89_scan_be_operation {
3711 	RTW89_SCAN_OP_STOP,
3712 	RTW89_SCAN_OP_START,
3713 	RTW89_SCAN_OP_SETPARM,
3714 	RTW89_SCAN_OP_GETRPT,
3715 	RTW89_SCAN_OP_NUM
3716 };
3717 
3718 enum rtw89_scan_be_mode {
3719 	RTW89_SCAN_MODE_SA,
3720 	RTW89_SCAN_MODE_MACC,
3721 	RTW89_SCAN_MODE_NUM
3722 };
3723 
3724 enum rtw89_scan_be_opmode {
3725 	RTW89_SCAN_OPMODE_NONE,
3726 	RTW89_SCAN_OPMODE_TBTT,
3727 	RTW89_SCAN_OPMODE_INTV,
3728 	RTW89_SCAN_OPMODE_CNT,
3729 	RTW89_SCAN_OPMODE_NUM,
3730 };
3731 
3732 struct rtw89_scan_option {
3733 	bool enable;
3734 	bool target_ch_mode;
3735 	u8 num_macc_role;
3736 	u8 num_opch;
3737 	u8 repeat;
3738 	u16 norm_pd;
3739 	u16 slow_pd;
3740 	u16 norm_cy;
3741 	u8 opch_end;
3742 	u16 delay;
3743 	u64 prohib_chan;
3744 	enum rtw89_phy_idx band;
3745 	enum rtw89_scan_be_operation operation;
3746 	enum rtw89_scan_be_mode scan_mode;
3747 	enum rtw89_mlo_dbcc_mode mlo_mode;
3748 };
3749 
3750 enum rtw89_qta_mode {
3751 	RTW89_QTA_SCC,
3752 	RTW89_QTA_DBCC,
3753 	RTW89_QTA_DLFW,
3754 	RTW89_QTA_WOW,
3755 
3756 	/* keep last */
3757 	RTW89_QTA_INVALID,
3758 };
3759 
3760 struct rtw89_hfc_ch_cfg {
3761 	u16 min;
3762 	u16 max;
3763 #define grp_0 0
3764 #define grp_1 1
3765 #define grp_num 2
3766 	u8 grp;
3767 };
3768 
3769 struct rtw89_hfc_ch_info {
3770 	u16 aval;
3771 	u16 used;
3772 };
3773 
3774 struct rtw89_hfc_pub_cfg {
3775 	u16 grp0;
3776 	u16 grp1;
3777 	u16 pub_max;
3778 	u16 wp_thrd;
3779 };
3780 
3781 struct rtw89_hfc_pub_info {
3782 	u16 g0_used;
3783 	u16 g1_used;
3784 	u16 g0_aval;
3785 	u16 g1_aval;
3786 	u16 pub_aval;
3787 	u16 wp_aval;
3788 };
3789 
3790 struct rtw89_hfc_prec_cfg {
3791 	u16 ch011_prec;
3792 	u16 h2c_prec;
3793 	u16 wp_ch07_prec;
3794 	u16 wp_ch811_prec;
3795 	u8 ch011_full_cond;
3796 	u8 h2c_full_cond;
3797 	u8 wp_ch07_full_cond;
3798 	u8 wp_ch811_full_cond;
3799 };
3800 
3801 struct rtw89_hfc_param {
3802 	bool en;
3803 	bool h2c_en;
3804 	u8 mode;
3805 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3806 	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3807 	struct rtw89_hfc_pub_cfg pub_cfg;
3808 	struct rtw89_hfc_pub_info pub_info;
3809 	struct rtw89_hfc_prec_cfg prec_cfg;
3810 };
3811 
3812 struct rtw89_hfc_param_ini {
3813 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3814 	const struct rtw89_hfc_pub_cfg *pub_cfg;
3815 	const struct rtw89_hfc_prec_cfg *prec_cfg;
3816 	u8 mode;
3817 };
3818 
3819 struct rtw89_dle_size {
3820 	u16 pge_size;
3821 	u16 lnk_pge_num;
3822 	u16 unlnk_pge_num;
3823 	/* for WiFi 7 chips below */
3824 	u32 srt_ofst;
3825 };
3826 
3827 struct rtw89_wde_quota {
3828 	u16 hif;
3829 	u16 wcpu;
3830 	u16 pkt_in;
3831 	u16 cpu_io;
3832 };
3833 
3834 struct rtw89_ple_quota {
3835 	u16 cma0_tx;
3836 	u16 cma1_tx;
3837 	u16 c2h;
3838 	u16 h2c;
3839 	u16 wcpu;
3840 	u16 mpdu_proc;
3841 	u16 cma0_dma;
3842 	u16 cma1_dma;
3843 	u16 bb_rpt;
3844 	u16 wd_rel;
3845 	u16 cpu_io;
3846 	u16 tx_rpt;
3847 	/* for WiFi 7 chips below */
3848 	u16 h2d;
3849 };
3850 
3851 struct rtw89_rsvd_quota {
3852 	u16 mpdu_info_tbl;
3853 	u16 b0_csi;
3854 	u16 b1_csi;
3855 	u16 b0_lmr;
3856 	u16 b1_lmr;
3857 	u16 b0_ftm;
3858 	u16 b1_ftm;
3859 	u16 b0_smr;
3860 	u16 b1_smr;
3861 	u16 others;
3862 };
3863 
3864 struct rtw89_dle_rsvd_size {
3865 	u32 srt_ofst;
3866 	u32 size;
3867 };
3868 
3869 struct rtw89_dle_mem {
3870 	enum rtw89_qta_mode mode;
3871 	const struct rtw89_dle_size *wde_size;
3872 	const struct rtw89_dle_size *ple_size;
3873 	const struct rtw89_wde_quota *wde_min_qt;
3874 	const struct rtw89_wde_quota *wde_max_qt;
3875 	const struct rtw89_ple_quota *ple_min_qt;
3876 	const struct rtw89_ple_quota *ple_max_qt;
3877 	/* for WiFi 7 chips below */
3878 	const struct rtw89_rsvd_quota *rsvd_qt;
3879 	const struct rtw89_dle_rsvd_size *rsvd0_size;
3880 	const struct rtw89_dle_rsvd_size *rsvd1_size;
3881 };
3882 
3883 struct rtw89_reg_def {
3884 	u32 addr;
3885 	u32 mask;
3886 };
3887 
3888 struct rtw89_reg2_def {
3889 	u32 addr;
3890 	u32 data;
3891 };
3892 
3893 struct rtw89_reg3_def {
3894 	u32 addr;
3895 	u32 mask;
3896 	u32 data;
3897 };
3898 
3899 struct rtw89_reg5_def {
3900 	u8 flag; /* recognized by parsers */
3901 	u8 path;
3902 	u32 addr;
3903 	u32 mask;
3904 	u32 data;
3905 };
3906 
3907 struct rtw89_reg_imr {
3908 	u32 addr;
3909 	u32 clr;
3910 	u32 set;
3911 };
3912 
3913 struct rtw89_phy_table {
3914 	const struct rtw89_reg2_def *regs;
3915 	u32 n_regs;
3916 	enum rtw89_rf_path rf_path;
3917 	void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3918 		       enum rtw89_rf_path rf_path, void *data);
3919 };
3920 
3921 struct rtw89_txpwr_table {
3922 	const void *data;
3923 	u32 size;
3924 	void (*load)(struct rtw89_dev *rtwdev,
3925 		     const struct rtw89_txpwr_table *tbl);
3926 };
3927 
3928 struct rtw89_txpwr_rule_2ghz {
3929 	const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3930 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3931 		       [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3932 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3933 			  [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3934 };
3935 
3936 struct rtw89_txpwr_rule_5ghz {
3937 	const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3938 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3939 		       [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3940 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3941 			  [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3942 };
3943 
3944 struct rtw89_txpwr_rule_6ghz {
3945 	const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3946 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3947 		       [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3948 		       [RTW89_6G_CH_NUM];
3949 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3950 			  [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3951 			  [RTW89_6G_CH_NUM];
3952 };
3953 
3954 struct rtw89_tx_shape {
3955 	const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3956 	const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3957 };
3958 
3959 struct rtw89_rfe_parms {
3960 	const struct rtw89_txpwr_table *byr_tbl;
3961 	struct rtw89_txpwr_rule_2ghz rule_2ghz;
3962 	struct rtw89_txpwr_rule_5ghz rule_5ghz;
3963 	struct rtw89_txpwr_rule_6ghz rule_6ghz;
3964 	struct rtw89_tx_shape tx_shape;
3965 };
3966 
3967 struct rtw89_rfe_parms_conf {
3968 	const struct rtw89_rfe_parms *rfe_parms;
3969 	u8 rfe_type;
3970 };
3971 
3972 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3973 
3974 struct rtw89_txpwr_conf {
3975 	u8 rfe_type;
3976 	u8 ent_sz;
3977 	u32 num_ents;
3978 	const void *data;
3979 };
3980 
rtw89_txpwr_entcpy(void * entry,const void * cursor,u8 size,const struct rtw89_txpwr_conf * conf)3981 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
3982 				      const struct rtw89_txpwr_conf *conf)
3983 {
3984 	u8 valid_size = min(size, conf->ent_sz);
3985 
3986 	memcpy(entry, cursor, valid_size);
3987 	return true;
3988 }
3989 
3990 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3991 
3992 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3993 	for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
3994 	     (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3995 	     (cursor) += (conf)->ent_sz) \
3996 		if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
3997 
3998 struct rtw89_txpwr_byrate_data {
3999 	struct rtw89_txpwr_conf conf;
4000 	struct rtw89_txpwr_table tbl;
4001 };
4002 
4003 struct rtw89_txpwr_lmt_2ghz_data {
4004 	struct rtw89_txpwr_conf conf;
4005 	s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4006 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4007 	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4008 };
4009 
4010 struct rtw89_txpwr_lmt_5ghz_data {
4011 	struct rtw89_txpwr_conf conf;
4012 	s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4013 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4014 	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4015 };
4016 
4017 struct rtw89_txpwr_lmt_6ghz_data {
4018 	struct rtw89_txpwr_conf conf;
4019 	s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4020 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4021 	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4022 	    [RTW89_6G_CH_NUM];
4023 };
4024 
4025 struct rtw89_txpwr_lmt_ru_2ghz_data {
4026 	struct rtw89_txpwr_conf conf;
4027 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4028 	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4029 };
4030 
4031 struct rtw89_txpwr_lmt_ru_5ghz_data {
4032 	struct rtw89_txpwr_conf conf;
4033 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4034 	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4035 };
4036 
4037 struct rtw89_txpwr_lmt_ru_6ghz_data {
4038 	struct rtw89_txpwr_conf conf;
4039 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4040 	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4041 	    [RTW89_6G_CH_NUM];
4042 };
4043 
4044 struct rtw89_tx_shape_lmt_data {
4045 	struct rtw89_txpwr_conf conf;
4046 	u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4047 };
4048 
4049 struct rtw89_tx_shape_lmt_ru_data {
4050 	struct rtw89_txpwr_conf conf;
4051 	u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4052 };
4053 
4054 struct rtw89_rfe_data {
4055 	struct rtw89_txpwr_byrate_data byrate;
4056 	struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4057 	struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4058 	struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4059 	struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4060 	struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4061 	struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4062 	struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4063 	struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4064 	struct rtw89_rfe_parms rfe_parms;
4065 };
4066 
4067 struct rtw89_page_regs {
4068 	u32 hci_fc_ctrl;
4069 	u32 ch_page_ctrl;
4070 	u32 ach_page_ctrl;
4071 	u32 ach_page_info;
4072 	u32 pub_page_info3;
4073 	u32 pub_page_ctrl1;
4074 	u32 pub_page_ctrl2;
4075 	u32 pub_page_info1;
4076 	u32 pub_page_info2;
4077 	u32 wp_page_ctrl1;
4078 	u32 wp_page_ctrl2;
4079 	u32 wp_page_info1;
4080 };
4081 
4082 struct rtw89_imr_info {
4083 	u32 wdrls_imr_set;
4084 	u32 wsec_imr_reg;
4085 	u32 wsec_imr_set;
4086 	u32 mpdu_tx_imr_set;
4087 	u32 mpdu_rx_imr_set;
4088 	u32 sta_sch_imr_set;
4089 	u32 txpktctl_imr_b0_reg;
4090 	u32 txpktctl_imr_b0_clr;
4091 	u32 txpktctl_imr_b0_set;
4092 	u32 txpktctl_imr_b1_reg;
4093 	u32 txpktctl_imr_b1_clr;
4094 	u32 txpktctl_imr_b1_set;
4095 	u32 wde_imr_clr;
4096 	u32 wde_imr_set;
4097 	u32 ple_imr_clr;
4098 	u32 ple_imr_set;
4099 	u32 host_disp_imr_clr;
4100 	u32 host_disp_imr_set;
4101 	u32 cpu_disp_imr_clr;
4102 	u32 cpu_disp_imr_set;
4103 	u32 other_disp_imr_clr;
4104 	u32 other_disp_imr_set;
4105 	u32 bbrpt_com_err_imr_reg;
4106 	u32 bbrpt_chinfo_err_imr_reg;
4107 	u32 bbrpt_err_imr_set;
4108 	u32 bbrpt_dfs_err_imr_reg;
4109 	u32 ptcl_imr_clr;
4110 	u32 ptcl_imr_set;
4111 	u32 cdma_imr_0_reg;
4112 	u32 cdma_imr_0_clr;
4113 	u32 cdma_imr_0_set;
4114 	u32 cdma_imr_1_reg;
4115 	u32 cdma_imr_1_clr;
4116 	u32 cdma_imr_1_set;
4117 	u32 phy_intf_imr_reg;
4118 	u32 phy_intf_imr_clr;
4119 	u32 phy_intf_imr_set;
4120 	u32 rmac_imr_reg;
4121 	u32 rmac_imr_clr;
4122 	u32 rmac_imr_set;
4123 	u32 tmac_imr_reg;
4124 	u32 tmac_imr_clr;
4125 	u32 tmac_imr_set;
4126 };
4127 
4128 struct rtw89_imr_table {
4129 	const struct rtw89_reg_imr *regs;
4130 	u32 n_regs;
4131 };
4132 
4133 struct rtw89_xtal_info {
4134 	u32 xcap_reg;
4135 	u32 sc_xo_mask;
4136 	u32 sc_xi_mask;
4137 };
4138 
4139 struct rtw89_rrsr_cfgs {
4140 	struct rtw89_reg3_def ref_rate;
4141 	struct rtw89_reg3_def rsc;
4142 };
4143 
4144 struct rtw89_rfkill_regs {
4145 	struct rtw89_reg3_def pinmux;
4146 	struct rtw89_reg3_def mode;
4147 };
4148 
4149 struct rtw89_dig_regs {
4150 	u32 seg0_pd_reg;
4151 	u32 pd_lower_bound_mask;
4152 	u32 pd_spatial_reuse_en;
4153 	u32 bmode_pd_reg;
4154 	u32 bmode_cca_rssi_limit_en;
4155 	u32 bmode_pd_lower_bound_reg;
4156 	u32 bmode_rssi_nocca_low_th_mask;
4157 	struct rtw89_reg_def p0_lna_init;
4158 	struct rtw89_reg_def p1_lna_init;
4159 	struct rtw89_reg_def p0_tia_init;
4160 	struct rtw89_reg_def p1_tia_init;
4161 	struct rtw89_reg_def p0_rxb_init;
4162 	struct rtw89_reg_def p1_rxb_init;
4163 	struct rtw89_reg_def p0_p20_pagcugc_en;
4164 	struct rtw89_reg_def p0_s20_pagcugc_en;
4165 	struct rtw89_reg_def p1_p20_pagcugc_en;
4166 	struct rtw89_reg_def p1_s20_pagcugc_en;
4167 };
4168 
4169 struct rtw89_edcca_regs {
4170 	u32 edcca_level;
4171 	u32 edcca_mask;
4172 	u32 edcca_p_mask;
4173 	u32 ppdu_level;
4174 	u32 ppdu_mask;
4175 	u32 rpt_a;
4176 	u32 rpt_b;
4177 	u32 rpt_sel;
4178 	u32 rpt_sel_mask;
4179 	u32 rpt_sel_be;
4180 	u32 rpt_sel_be_mask;
4181 	u32 tx_collision_t2r_st;
4182 	u32 tx_collision_t2r_st_mask;
4183 };
4184 
4185 struct rtw89_phy_ul_tb_info {
4186 	bool dyn_tb_tri_en;
4187 	u8 def_if_bandedge;
4188 };
4189 
4190 struct rtw89_antdiv_stats {
4191 	struct ewma_rssi cck_rssi_avg;
4192 	struct ewma_rssi ofdm_rssi_avg;
4193 	struct ewma_rssi non_legacy_rssi_avg;
4194 	u16 pkt_cnt_cck;
4195 	u16 pkt_cnt_ofdm;
4196 	u16 pkt_cnt_non_legacy;
4197 	u32 evm;
4198 };
4199 
4200 struct rtw89_antdiv_info {
4201 	struct rtw89_antdiv_stats target_stats;
4202 	struct rtw89_antdiv_stats main_stats;
4203 	struct rtw89_antdiv_stats aux_stats;
4204 	u8 training_count;
4205 	u8 rssi_pre;
4206 	bool get_stats;
4207 };
4208 
4209 enum rtw89_chanctx_state {
4210 	RTW89_CHANCTX_STATE_MCC_START,
4211 	RTW89_CHANCTX_STATE_MCC_STOP,
4212 };
4213 
4214 enum rtw89_chanctx_callbacks {
4215 	RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4216 	RTW89_CHANCTX_CALLBACK_RFK,
4217 
4218 	NUM_OF_RTW89_CHANCTX_CALLBACKS,
4219 };
4220 
4221 struct rtw89_chanctx_listener {
4222 	void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4223 		(struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4224 };
4225 
4226 struct rtw89_chip_info {
4227 	enum rtw89_core_chip_id chip_id;
4228 	enum rtw89_chip_gen chip_gen;
4229 	const struct rtw89_chip_ops *ops;
4230 	const struct rtw89_mac_gen_def *mac_def;
4231 	const struct rtw89_phy_gen_def *phy_def;
4232 	const char *fw_basename;
4233 	u8 fw_format_max;
4234 	bool try_ce_fw;
4235 	u8 bbmcu_nr;
4236 	u32 needed_fw_elms;
4237 	u32 fifo_size;
4238 	bool small_fifo_size;
4239 	u32 dle_scc_rsvd_size;
4240 	u16 max_amsdu_limit;
4241 	bool dis_2g_40m_ul_ofdma;
4242 	u32 rsvd_ple_ofst;
4243 	const struct rtw89_hfc_param_ini *hfc_param_ini;
4244 	const struct rtw89_dle_mem *dle_mem;
4245 	u8 wde_qempty_acq_grpnum;
4246 	u8 wde_qempty_mgq_grpsel;
4247 	u32 rf_base_addr[2];
4248 	u8 support_macid_num;
4249 	u8 support_link_num;
4250 	u8 support_chanctx_num;
4251 	u8 support_bands;
4252 	u16 support_bandwidths;
4253 	bool support_unii4;
4254 	bool support_rnr;
4255 	bool ul_tb_waveform_ctrl;
4256 	bool ul_tb_pwr_diff;
4257 	bool hw_sec_hdr;
4258 	bool hw_mgmt_tx_encrypt;
4259 	u8 rf_path_num;
4260 	u8 tx_nss;
4261 	u8 rx_nss;
4262 	u8 acam_num;
4263 	u8 bcam_num;
4264 	u8 scam_num;
4265 	u8 bacam_num;
4266 	u8 bacam_dynamic_num;
4267 	enum rtw89_bacam_ver bacam_ver;
4268 	u8 ppdu_max_usr;
4269 
4270 	u8 sec_ctrl_efuse_size;
4271 	u32 physical_efuse_size;
4272 	u32 logical_efuse_size;
4273 	u32 limit_efuse_size;
4274 	u32 dav_phy_efuse_size;
4275 	u32 dav_log_efuse_size;
4276 	u32 phycap_addr;
4277 	u32 phycap_size;
4278 	const struct rtw89_efuse_block_cfg *efuse_blocks;
4279 
4280 	const struct rtw89_pwr_cfg * const *pwr_on_seq;
4281 	const struct rtw89_pwr_cfg * const *pwr_off_seq;
4282 	const struct rtw89_phy_table *bb_table;
4283 	const struct rtw89_phy_table *bb_gain_table;
4284 	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4285 	const struct rtw89_phy_table *nctl_table;
4286 	const struct rtw89_rfk_tbl *nctl_post_table;
4287 	const struct rtw89_phy_dig_gain_table *dig_table;
4288 	const struct rtw89_dig_regs *dig_regs;
4289 	const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4290 
4291 	/* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4292 	const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4293 	const struct rtw89_rfe_parms *dflt_parms;
4294 	const struct rtw89_chanctx_listener *chanctx_listener;
4295 
4296 	u8 txpwr_factor_rf;
4297 	u8 txpwr_factor_mac;
4298 
4299 	u32 para_ver;
4300 	u32 wlcx_desired;
4301 	u8 btcx_desired;
4302 	u8 scbd;
4303 	u8 mailbox;
4304 
4305 	u8 afh_guard_ch;
4306 	const u8 *wl_rssi_thres;
4307 	const u8 *bt_rssi_thres;
4308 	u8 rssi_tol;
4309 
4310 	u8 mon_reg_num;
4311 	const struct rtw89_btc_fbtc_mreg *mon_reg;
4312 	u8 rf_para_ulink_num;
4313 	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4314 	u8 rf_para_dlink_num;
4315 	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4316 	u8 ps_mode_supported;
4317 	u8 low_power_hci_modes;
4318 
4319 	u32 h2c_cctl_func_id;
4320 	u32 hci_func_en_addr;
4321 	u32 h2c_desc_size;
4322 	u32 txwd_body_size;
4323 	u32 txwd_info_size;
4324 	u32 h2c_ctrl_reg;
4325 	const u32 *h2c_regs;
4326 	struct rtw89_reg_def h2c_counter_reg;
4327 	u32 c2h_ctrl_reg;
4328 	const u32 *c2h_regs;
4329 	struct rtw89_reg_def c2h_counter_reg;
4330 	const struct rtw89_page_regs *page_regs;
4331 	const u32 *wow_reason_reg;
4332 	bool cfo_src_fd;
4333 	bool cfo_hw_comp;
4334 	const struct rtw89_reg_def *dcfo_comp;
4335 	u8 dcfo_comp_sft;
4336 	const struct rtw89_imr_info *imr_info;
4337 	const struct rtw89_imr_table *imr_dmac_table;
4338 	const struct rtw89_imr_table *imr_cmac_table;
4339 	const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4340 	struct rtw89_reg_def bss_clr_vld;
4341 	u32 bss_clr_map_reg;
4342 	const struct rtw89_rfkill_regs *rfkill_init;
4343 	struct rtw89_reg_def rfkill_get;
4344 	u32 dma_ch_mask;
4345 	const struct rtw89_edcca_regs *edcca_regs;
4346 	const struct wiphy_wowlan_support *wowlan_stub;
4347 	const struct rtw89_xtal_info *xtal_info;
4348 };
4349 
4350 union rtw89_bus_info {
4351 	const struct rtw89_pci_info *pci;
4352 };
4353 
4354 struct rtw89_driver_info {
4355 	const struct rtw89_chip_info *chip;
4356 	const struct dmi_system_id *quirks;
4357 	union rtw89_bus_info bus;
4358 };
4359 
4360 enum rtw89_hcifc_mode {
4361 	RTW89_HCIFC_POH = 0,
4362 	RTW89_HCIFC_STF = 1,
4363 	RTW89_HCIFC_SDIO = 2,
4364 
4365 	/* keep last */
4366 	RTW89_HCIFC_MODE_INVALID,
4367 };
4368 
4369 struct rtw89_dle_info {
4370 	const struct rtw89_rsvd_quota *rsvd_qt;
4371 	enum rtw89_qta_mode qta_mode;
4372 	u16 ple_pg_size;
4373 	u16 ple_free_pg;
4374 	u16 c0_rx_qta;
4375 	u16 c1_rx_qta;
4376 };
4377 
4378 enum rtw89_host_rpr_mode {
4379 	RTW89_RPR_MODE_POH = 0,
4380 	RTW89_RPR_MODE_STF
4381 };
4382 
4383 #define RTW89_COMPLETION_BUF_SIZE 40
4384 #define RTW89_WAIT_COND_IDLE UINT_MAX
4385 
4386 struct rtw89_completion_data {
4387 	bool err;
4388 	u8 buf[RTW89_COMPLETION_BUF_SIZE];
4389 };
4390 
4391 struct rtw89_wait_info {
4392 	atomic_t cond;
4393 	struct completion completion;
4394 	struct rtw89_completion_data data;
4395 };
4396 
4397 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4398 
rtw89_init_wait(struct rtw89_wait_info * wait)4399 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4400 {
4401 	init_completion(&wait->completion);
4402 	atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4403 }
4404 
4405 struct rtw89_mac_info {
4406 	struct rtw89_dle_info dle_info;
4407 	struct rtw89_hfc_param hfc_param;
4408 	enum rtw89_qta_mode qta_mode;
4409 	u8 rpwm_seq_num;
4410 	u8 cpwm_seq_num;
4411 
4412 	/* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4413 	struct rtw89_wait_info fw_ofld_wait;
4414 	/* see RTW89_PS_WAIT_COND series for wait condition */
4415 	struct rtw89_wait_info ps_wait;
4416 };
4417 
4418 enum rtw89_fwdl_check_type {
4419 	RTW89_FWDL_CHECK_FREERTOS_DONE,
4420 	RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4421 	RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4422 	RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4423 	RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4424 };
4425 
4426 enum rtw89_fw_type {
4427 	RTW89_FW_NORMAL = 1,
4428 	RTW89_FW_WOWLAN = 3,
4429 	RTW89_FW_NORMAL_CE = 5,
4430 	RTW89_FW_BBMCU0 = 64,
4431 	RTW89_FW_BBMCU1 = 65,
4432 	RTW89_FW_LOGFMT = 255,
4433 };
4434 
4435 enum rtw89_fw_feature {
4436 	RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4437 	RTW89_FW_FEATURE_SCAN_OFFLOAD,
4438 	RTW89_FW_FEATURE_TX_WAKE,
4439 	RTW89_FW_FEATURE_CRASH_TRIGGER,
4440 	RTW89_FW_FEATURE_NO_PACKET_DROP,
4441 	RTW89_FW_FEATURE_NO_DEEP_PS,
4442 	RTW89_FW_FEATURE_NO_LPS_PG,
4443 	RTW89_FW_FEATURE_BEACON_FILTER,
4444 	RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4445 	RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4446 	RTW89_FW_FEATURE_WOW_REASON_V1,
4447 	RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4448 };
4449 
4450 struct rtw89_fw_suit {
4451 	enum rtw89_fw_type type;
4452 	const u8 *data;
4453 	u32 size;
4454 	u8 major_ver;
4455 	u8 minor_ver;
4456 	u8 sub_ver;
4457 	u8 sub_idex;
4458 	u16 build_year;
4459 	u16 build_mon;
4460 	u16 build_date;
4461 	u16 build_hour;
4462 	u16 build_min;
4463 	u8 cmd_ver;
4464 	u8 hdr_ver;
4465 	u32 commitid;
4466 };
4467 
4468 #define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
4469 	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4470 #define RTW89_FW_SUIT_VER_CODE(s)	\
4471 	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4472 
4473 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr)		\
4474 	RTW89_FW_VER_CODE((mfw_hdr)->ver.major,	\
4475 			  (mfw_hdr)->ver.minor,	\
4476 			  (mfw_hdr)->ver.sub,	\
4477 			  (mfw_hdr)->ver.idx)
4478 
4479 #define RTW89_FW_HDR_VER_CODE(fw_hdr)				\
4480 	RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION),	\
4481 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION),	\
4482 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION),	\
4483 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4484 
4485 struct rtw89_fw_req_info {
4486 	const struct firmware *firmware;
4487 	struct completion completion;
4488 };
4489 
4490 struct rtw89_fw_log {
4491 	struct rtw89_fw_suit suit;
4492 	bool enable;
4493 	u32 last_fmt_id;
4494 	u32 fmt_count;
4495 	const __le32 *fmt_ids;
4496 	const char *(*fmts)[];
4497 };
4498 
4499 struct rtw89_fw_elm_info {
4500 	struct rtw89_phy_table *bb_tbl;
4501 	struct rtw89_phy_table *bb_gain;
4502 	struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4503 	struct rtw89_phy_table *rf_nctl;
4504 	struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4505 	struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4506 };
4507 
4508 enum rtw89_fw_mss_dev_type {
4509 	RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4510 	RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4511 };
4512 
4513 struct rtw89_fw_secure {
4514 	bool secure_boot;
4515 	u32 sb_sel_mgn;
4516 	u8 mss_dev_type;
4517 	u8 mss_cust_idx;
4518 	u8 mss_key_num;
4519 };
4520 
4521 struct rtw89_fw_info {
4522 	struct rtw89_fw_req_info req;
4523 	int fw_format;
4524 	u8 h2c_seq;
4525 	u8 rec_seq;
4526 	u8 h2c_counter;
4527 	u8 c2h_counter;
4528 	struct rtw89_fw_suit normal;
4529 	struct rtw89_fw_suit wowlan;
4530 	struct rtw89_fw_suit bbmcu0;
4531 	struct rtw89_fw_suit bbmcu1;
4532 	struct rtw89_fw_log log;
4533 	u32 feature_map;
4534 	struct rtw89_fw_elm_info elm_info;
4535 	struct rtw89_fw_secure sec;
4536 };
4537 
4538 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4539 	(!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4540 
4541 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4542 	((_fw)->feature_map |= BIT(_fw_feature))
4543 
4544 struct rtw89_cam_info {
4545 	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4546 	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4547 	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4548 	DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4549 	struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4550 	const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4551 };
4552 
4553 enum rtw89_sar_sources {
4554 	RTW89_SAR_SOURCE_NONE,
4555 	RTW89_SAR_SOURCE_COMMON,
4556 
4557 	RTW89_SAR_SOURCE_NR,
4558 };
4559 
4560 enum rtw89_sar_subband {
4561 	RTW89_SAR_2GHZ_SUBBAND,
4562 	RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4563 	RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4564 	RTW89_SAR_5GHZ_SUBBAND_3,   /* U-NII-3 */
4565 	RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4566 	RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4567 	RTW89_SAR_6GHZ_SUBBAND_6,   /* U-NII-6 */
4568 	RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4569 	RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4570 	RTW89_SAR_6GHZ_SUBBAND_8,   /* U-NII-8 */
4571 
4572 	RTW89_SAR_SUBBAND_NR,
4573 };
4574 
4575 struct rtw89_sar_cfg_common {
4576 	bool set[RTW89_SAR_SUBBAND_NR];
4577 	s32 cfg[RTW89_SAR_SUBBAND_NR];
4578 };
4579 
4580 struct rtw89_sar_info {
4581 	/* used to decide how to acces SAR cfg union */
4582 	enum rtw89_sar_sources src;
4583 
4584 	/* reserved for different knids of SAR cfg struct.
4585 	 * supposed that a single cfg struct cannot handle various SAR sources.
4586 	 */
4587 	union {
4588 		struct rtw89_sar_cfg_common cfg_common;
4589 	};
4590 };
4591 
4592 enum rtw89_tas_state {
4593 	RTW89_TAS_STATE_DPR_OFF,
4594 	RTW89_TAS_STATE_DPR_ON,
4595 	RTW89_TAS_STATE_DPR_FORBID,
4596 };
4597 
4598 #define RTW89_TAS_MAX_WINDOW 50
4599 struct rtw89_tas_info {
4600 	s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4601 	s32 total_txpwr;
4602 	u8 cur_idx;
4603 	s8 dpr_gap;
4604 	s8 delta;
4605 	enum rtw89_tas_state state;
4606 	bool enable;
4607 };
4608 
4609 struct rtw89_chanctx_cfg {
4610 	enum rtw89_chanctx_idx idx;
4611 	int ref_count;
4612 };
4613 
4614 enum rtw89_chanctx_changes {
4615 	RTW89_CHANCTX_REMOTE_STA_CHANGE,
4616 	RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4617 	RTW89_CHANCTX_P2P_PS_CHANGE,
4618 	RTW89_CHANCTX_BT_SLOT_CHANGE,
4619 	RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4620 
4621 	NUM_OF_RTW89_CHANCTX_CHANGES,
4622 	RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4623 };
4624 
4625 enum rtw89_entity_mode {
4626 	RTW89_ENTITY_MODE_SCC,
4627 	RTW89_ENTITY_MODE_MCC_PREPARE,
4628 	RTW89_ENTITY_MODE_MCC,
4629 
4630 	NUM_OF_RTW89_ENTITY_MODE,
4631 	RTW89_ENTITY_MODE_INVALID = -EINVAL,
4632 	RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4633 };
4634 
4635 struct rtw89_chanctx {
4636 	struct cfg80211_chan_def chandef;
4637 	struct rtw89_chan chan;
4638 	struct rtw89_chan_rcd rcd;
4639 
4640 	/* only assigned when running with chanctx_ops */
4641 	struct rtw89_chanctx_cfg *cfg;
4642 };
4643 
4644 struct rtw89_edcca_bak {
4645 	u8 a;
4646 	u8 p;
4647 	u8 ppdu;
4648 	u8 th_old;
4649 };
4650 
4651 enum rtw89_dm_type {
4652 	RTW89_DM_DYNAMIC_EDCCA,
4653 };
4654 
4655 struct rtw89_hal {
4656 	u32 rx_fltr;
4657 	u8 cv;
4658 	u8 acv;
4659 	u32 antenna_tx;
4660 	u32 antenna_rx;
4661 	u8 tx_nss;
4662 	u8 rx_nss;
4663 	bool tx_path_diversity;
4664 	bool ant_diversity;
4665 	bool ant_diversity_fixed;
4666 	bool support_cckpd;
4667 	bool support_igi;
4668 	atomic_t roc_chanctx_idx;
4669 
4670 	DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4671 	DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
4672 	struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
4673 	struct cfg80211_chan_def roc_chandef;
4674 
4675 	bool entity_active;
4676 	bool entity_pause;
4677 	enum rtw89_entity_mode entity_mode;
4678 
4679 	struct rtw89_edcca_bak edcca_bak;
4680 	u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4681 };
4682 
4683 #define RTW89_MAX_MAC_ID_NUM 128
4684 #define RTW89_MAX_PKT_OFLD_NUM 255
4685 
4686 enum rtw89_flags {
4687 	RTW89_FLAG_POWERON,
4688 	RTW89_FLAG_DMAC_FUNC,
4689 	RTW89_FLAG_CMAC0_FUNC,
4690 	RTW89_FLAG_CMAC1_FUNC,
4691 	RTW89_FLAG_FW_RDY,
4692 	RTW89_FLAG_RUNNING,
4693 	RTW89_FLAG_PROBE_DONE,
4694 	RTW89_FLAG_BFEE_MON,
4695 	RTW89_FLAG_BFEE_EN,
4696 	RTW89_FLAG_BFEE_TIMER_KEEP,
4697 	RTW89_FLAG_NAPI_RUNNING,
4698 	RTW89_FLAG_LEISURE_PS,
4699 	RTW89_FLAG_LOW_POWER_MODE,
4700 	RTW89_FLAG_INACTIVE_PS,
4701 	RTW89_FLAG_CRASH_SIMULATING,
4702 	RTW89_FLAG_SER_HANDLING,
4703 	RTW89_FLAG_WOWLAN,
4704 	RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4705 	RTW89_FLAG_CHANGING_INTERFACE,
4706 	RTW89_FLAG_HW_RFKILL_STATE,
4707 
4708 	NUM_OF_RTW89_FLAGS,
4709 };
4710 
4711 enum rtw89_quirks {
4712 	RTW89_QUIRK_PCI_BER,
4713 
4714 	NUM_OF_RTW89_QUIRKS,
4715 };
4716 
4717 enum rtw89_pkt_drop_sel {
4718 	RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4719 	RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4720 	RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4721 	RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4722 	RTW89_PKT_DROP_SEL_MACID_ALL,
4723 	RTW89_PKT_DROP_SEL_MG0_ONCE,
4724 	RTW89_PKT_DROP_SEL_HIQ_ONCE,
4725 	RTW89_PKT_DROP_SEL_HIQ_PORT,
4726 	RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4727 	RTW89_PKT_DROP_SEL_BAND,
4728 	RTW89_PKT_DROP_SEL_BAND_ONCE,
4729 	RTW89_PKT_DROP_SEL_REL_MACID,
4730 	RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4731 	RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4732 };
4733 
4734 struct rtw89_pkt_drop_params {
4735 	enum rtw89_pkt_drop_sel sel;
4736 	enum rtw89_mac_idx mac_band;
4737 	u8 macid;
4738 	u8 port;
4739 	u8 mbssid;
4740 	bool tf_trs;
4741 	u32 macid_band_sel[4];
4742 };
4743 
4744 struct rtw89_pkt_stat {
4745 	u16 beacon_nr;
4746 	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4747 };
4748 
4749 DECLARE_EWMA(thermal, 4, 4);
4750 
4751 struct rtw89_phy_stat {
4752 	struct ewma_thermal avg_thermal[RF_PATH_MAX];
4753 	struct rtw89_pkt_stat cur_pkt_stat;
4754 	struct rtw89_pkt_stat last_pkt_stat;
4755 };
4756 
4757 enum rtw89_rfk_report_state {
4758 	RTW89_RFK_STATE_START = 0x0,
4759 	RTW89_RFK_STATE_OK = 0x1,
4760 	RTW89_RFK_STATE_FAIL = 0x2,
4761 	RTW89_RFK_STATE_TIMEOUT = 0x3,
4762 	RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4763 };
4764 
4765 struct rtw89_rfk_wait_info {
4766 	struct completion completion;
4767 	ktime_t start_time;
4768 	enum rtw89_rfk_report_state state;
4769 	u8 version;
4770 };
4771 
4772 #define RTW89_DACK_PATH_NR 2
4773 #define RTW89_DACK_IDX_NR 2
4774 #define RTW89_DACK_MSBK_NR 16
4775 struct rtw89_dack_info {
4776 	bool dack_done;
4777 	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4778 	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4779 	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4780 	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4781 	u32 dack_cnt;
4782 	bool addck_timeout[RTW89_DACK_PATH_NR];
4783 	bool dadck_timeout[RTW89_DACK_PATH_NR];
4784 	bool msbk_timeout[RTW89_DACK_PATH_NR];
4785 };
4786 
4787 enum rtw89_rfk_chs_nrs {
4788 	__RTW89_RFK_CHS_NR_V0 = 2,
4789 	__RTW89_RFK_CHS_NR_V1 = 3,
4790 
4791 	RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
4792 };
4793 
4794 struct rtw89_rfk_mcc_info {
4795 	u8 ch[RTW89_RFK_CHS_NR];
4796 	u8 band[RTW89_RFK_CHS_NR];
4797 	u8 bw[RTW89_RFK_CHS_NR];
4798 	u8 table_idx;
4799 };
4800 
4801 #define RTW89_IQK_CHS_NR 2
4802 #define RTW89_IQK_PATH_NR 4
4803 
4804 struct rtw89_lck_info {
4805 	u8 thermal[RF_PATH_MAX];
4806 };
4807 
4808 struct rtw89_rx_dck_info {
4809 	u8 thermal[RF_PATH_MAX];
4810 };
4811 
4812 struct rtw89_iqk_info {
4813 	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4814 	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4815 	bool lok_fail[RTW89_IQK_PATH_NR];
4816 	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4817 	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4818 	u32 iqk_fail_cnt;
4819 	bool is_iqk_init;
4820 	u32 iqk_channel[RTW89_IQK_CHS_NR];
4821 	u8 iqk_band[RTW89_IQK_PATH_NR];
4822 	u8 iqk_ch[RTW89_IQK_PATH_NR];
4823 	u8 iqk_bw[RTW89_IQK_PATH_NR];
4824 	u8 iqk_times;
4825 	u8 version;
4826 	u32 nb_txcfir[RTW89_IQK_PATH_NR];
4827 	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4828 	u32 bp_txkresult[RTW89_IQK_PATH_NR];
4829 	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4830 	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4831 	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4832 	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4833 	bool is_nbiqk;
4834 	bool iqk_fft_en;
4835 	bool iqk_xym_en;
4836 	bool iqk_sram_en;
4837 	bool iqk_cfir_en;
4838 	u32 syn1to2;
4839 	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4840 	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4841 	u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4842 	u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4843 };
4844 
4845 #define RTW89_DPK_RF_PATH 2
4846 #define RTW89_DPK_AVG_THERMAL_NUM 8
4847 #define RTW89_DPK_BKUP_NUM 2
4848 struct rtw89_dpk_bkup_para {
4849 	enum rtw89_band band;
4850 	enum rtw89_bandwidth bw;
4851 	u8 ch;
4852 	bool path_ok;
4853 	u8 mdpd_en;
4854 	u8 txagc_dpk;
4855 	u8 ther_dpk;
4856 	u8 gs;
4857 	u16 pwsf;
4858 };
4859 
4860 struct rtw89_dpk_info {
4861 	bool is_dpk_enable;
4862 	bool is_dpk_reload_en;
4863 	u8 dpk_gs[RTW89_PHY_MAX];
4864 	u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4865 	u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4866 	u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4867 	u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4868 	u8 cur_idx[RTW89_DPK_RF_PATH];
4869 	u8 cur_k_set;
4870 	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4871 	u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
4872 	u32 dpk_order[RTW89_DPK_RF_PATH];
4873 };
4874 
4875 struct rtw89_fem_info {
4876 	bool elna_2g;
4877 	bool elna_5g;
4878 	bool epa_2g;
4879 	bool epa_5g;
4880 	bool epa_6g;
4881 };
4882 
4883 struct rtw89_phy_ch_info {
4884 	u8 rssi_min;
4885 	u16 rssi_min_macid;
4886 	u8 pre_rssi_min;
4887 	u8 rssi_max;
4888 	u16 rssi_max_macid;
4889 	u8 rxsc_160;
4890 	u8 rxsc_80;
4891 	u8 rxsc_40;
4892 	u8 rxsc_20;
4893 	u8 rxsc_l;
4894 	u8 is_noisy;
4895 };
4896 
4897 struct rtw89_agc_gaincode_set {
4898 	u8 lna_idx;
4899 	u8 tia_idx;
4900 	u8 rxb_idx;
4901 };
4902 
4903 #define IGI_RSSI_TH_NUM 5
4904 #define FA_TH_NUM 4
4905 #define LNA_GAIN_NUM 7
4906 #define TIA_GAIN_NUM 2
4907 struct rtw89_dig_info {
4908 	struct rtw89_agc_gaincode_set cur_gaincode;
4909 	bool force_gaincode_idx_en;
4910 	struct rtw89_agc_gaincode_set force_gaincode;
4911 	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4912 	u16 fa_th[FA_TH_NUM];
4913 	u8 igi_rssi;
4914 	u8 igi_fa_rssi;
4915 	u8 fa_rssi_ofst;
4916 	u8 dyn_igi_max;
4917 	u8 dyn_igi_min;
4918 	bool dyn_pd_th_en;
4919 	u8 dyn_pd_th_max;
4920 	u8 pd_low_th_ofst;
4921 	u8 ib_pbk;
4922 	s8 ib_pkpwr;
4923 	s8 lna_gain_a[LNA_GAIN_NUM];
4924 	s8 lna_gain_g[LNA_GAIN_NUM];
4925 	s8 *lna_gain;
4926 	s8 tia_gain_a[TIA_GAIN_NUM];
4927 	s8 tia_gain_g[TIA_GAIN_NUM];
4928 	s8 *tia_gain;
4929 	bool is_linked_pre;
4930 	bool bypass_dig;
4931 };
4932 
4933 enum rtw89_multi_cfo_mode {
4934 	RTW89_PKT_BASED_AVG_MODE = 0,
4935 	RTW89_ENTRY_BASED_AVG_MODE = 1,
4936 	RTW89_TP_BASED_AVG_MODE = 2,
4937 };
4938 
4939 enum rtw89_phy_cfo_status {
4940 	RTW89_PHY_DCFO_STATE_NORMAL = 0,
4941 	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4942 	RTW89_PHY_DCFO_STATE_HOLD = 2,
4943 	RTW89_PHY_DCFO_STATE_MAX
4944 };
4945 
4946 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4947 	RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4948 	RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4949 };
4950 
4951 struct rtw89_cfo_tracking_info {
4952 	u16 cfo_timer_ms;
4953 	bool cfo_trig_by_timer_en;
4954 	enum rtw89_phy_cfo_status phy_cfo_status;
4955 	enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4956 	u8 phy_cfo_trk_cnt;
4957 	bool is_adjust;
4958 	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4959 	bool apply_compensation;
4960 	u8 crystal_cap;
4961 	u8 crystal_cap_default;
4962 	u8 def_x_cap;
4963 	s8 x_cap_ofst;
4964 	u32 sta_cfo_tolerance;
4965 	s32 cfo_tail[CFO_TRACK_MAX_USER];
4966 	u16 cfo_cnt[CFO_TRACK_MAX_USER];
4967 	s32 cfo_avg_pre;
4968 	s32 cfo_avg[CFO_TRACK_MAX_USER];
4969 	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4970 	s32 dcfo_avg;
4971 	s32 dcfo_avg_pre;
4972 	u32 packet_count;
4973 	u32 packet_count_pre;
4974 	s32 residual_cfo_acc;
4975 	u8 phy_cfotrk_state;
4976 	u8 phy_cfotrk_cnt;
4977 	bool divergence_lock_en;
4978 	u8 x_cap_lb;
4979 	u8 x_cap_ub;
4980 	u8 lock_cnt;
4981 };
4982 
4983 enum rtw89_tssi_mode {
4984 	RTW89_TSSI_NORMAL = 0,
4985 	RTW89_TSSI_SCAN = 1,
4986 };
4987 
4988 enum rtw89_tssi_alimk_band {
4989 	TSSI_ALIMK_2G = 0,
4990 	TSSI_ALIMK_5GL,
4991 	TSSI_ALIMK_5GM,
4992 	TSSI_ALIMK_5GH,
4993 	TSSI_ALIMK_MAX
4994 };
4995 
4996 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4997 #define TSSI_TRIM_CH_GROUP_NUM 8
4998 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4999 
5000 #define TSSI_CCK_CH_GROUP_NUM 6
5001 #define TSSI_MCS_2G_CH_GROUP_NUM 5
5002 #define TSSI_MCS_5G_CH_GROUP_NUM 14
5003 #define TSSI_MCS_6G_CH_GROUP_NUM 32
5004 #define TSSI_MCS_CH_GROUP_NUM \
5005 	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5006 #define TSSI_MAX_CH_NUM 67
5007 #define TSSI_ALIMK_VALUE_NUM 8
5008 
5009 struct rtw89_tssi_info {
5010 	u8 thermal[RF_PATH_MAX];
5011 	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5012 	s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5013 	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5014 	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5015 	s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5016 	s8 extra_ofst[RF_PATH_MAX];
5017 	bool tssi_tracking_check[RF_PATH_MAX];
5018 	u8 default_txagc_offset[RF_PATH_MAX];
5019 	u32 base_thermal[RF_PATH_MAX];
5020 	bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5021 	u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5022 	u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5023 	bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5024 	u32 tssi_alimk_time;
5025 };
5026 
5027 struct rtw89_power_trim_info {
5028 	bool pg_thermal_trim;
5029 	bool pg_pa_bias_trim;
5030 	u8 thermal_trim[RF_PATH_MAX];
5031 	u8 pa_bias_trim[RF_PATH_MAX];
5032 	u8 pad_bias_trim[RF_PATH_MAX];
5033 };
5034 
5035 struct rtw89_regd {
5036 	char alpha2[3];
5037 	u8 txpwr_regd[RTW89_BAND_NUM];
5038 };
5039 
5040 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5041 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5042 #define RTW89_5GHZ_UNII4_START_INDEX 25
5043 
5044 struct rtw89_regulatory_info {
5045 	const struct rtw89_regd *regd;
5046 	enum rtw89_reg_6ghz_power reg_6ghz_power;
5047 	struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5048 	DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5049 	DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5050 	DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5051 };
5052 
5053 enum rtw89_ifs_clm_application {
5054 	RTW89_IFS_CLM_INIT = 0,
5055 	RTW89_IFS_CLM_BACKGROUND = 1,
5056 	RTW89_IFS_CLM_ACS = 2,
5057 	RTW89_IFS_CLM_DIG = 3,
5058 	RTW89_IFS_CLM_TDMA_DIG = 4,
5059 	RTW89_IFS_CLM_DBG = 5,
5060 	RTW89_IFS_CLM_DBG_MANUAL = 6
5061 };
5062 
5063 enum rtw89_env_racing_lv {
5064 	RTW89_RAC_RELEASE = 0,
5065 	RTW89_RAC_LV_1 = 1,
5066 	RTW89_RAC_LV_2 = 2,
5067 	RTW89_RAC_LV_3 = 3,
5068 	RTW89_RAC_LV_4 = 4,
5069 	RTW89_RAC_MAX_NUM = 5
5070 };
5071 
5072 struct rtw89_ccx_para_info {
5073 	enum rtw89_env_racing_lv rac_lv;
5074 	u16 mntr_time;
5075 	u8 nhm_manual_th_ofst;
5076 	u8 nhm_manual_th0;
5077 	enum rtw89_ifs_clm_application ifs_clm_app;
5078 	u32 ifs_clm_manual_th_times;
5079 	u32 ifs_clm_manual_th0;
5080 	u8 fahm_manual_th_ofst;
5081 	u8 fahm_manual_th0;
5082 	u8 fahm_numer_opt;
5083 	u8 fahm_denom_opt;
5084 };
5085 
5086 enum rtw89_ccx_edcca_opt_sc_idx {
5087 	RTW89_CCX_EDCCA_SEG0_P0 = 0,
5088 	RTW89_CCX_EDCCA_SEG0_S1 = 1,
5089 	RTW89_CCX_EDCCA_SEG0_S2 = 2,
5090 	RTW89_CCX_EDCCA_SEG0_S3 = 3,
5091 	RTW89_CCX_EDCCA_SEG1_P0 = 4,
5092 	RTW89_CCX_EDCCA_SEG1_S1 = 5,
5093 	RTW89_CCX_EDCCA_SEG1_S2 = 6,
5094 	RTW89_CCX_EDCCA_SEG1_S3 = 7
5095 };
5096 
5097 enum rtw89_ccx_edcca_opt_bw_idx {
5098 	RTW89_CCX_EDCCA_BW20_0 = 0,
5099 	RTW89_CCX_EDCCA_BW20_1 = 1,
5100 	RTW89_CCX_EDCCA_BW20_2 = 2,
5101 	RTW89_CCX_EDCCA_BW20_3 = 3,
5102 	RTW89_CCX_EDCCA_BW20_4 = 4,
5103 	RTW89_CCX_EDCCA_BW20_5 = 5,
5104 	RTW89_CCX_EDCCA_BW20_6 = 6,
5105 	RTW89_CCX_EDCCA_BW20_7 = 7
5106 };
5107 
5108 #define RTW89_NHM_TH_NUM 11
5109 #define RTW89_FAHM_TH_NUM 11
5110 #define RTW89_NHM_RPT_NUM 12
5111 #define RTW89_FAHM_RPT_NUM 12
5112 #define RTW89_IFS_CLM_NUM 4
5113 struct rtw89_env_monitor_info {
5114 	u8 ccx_watchdog_result;
5115 	bool ccx_ongoing;
5116 	u8 ccx_rac_lv;
5117 	bool ccx_manual_ctrl;
5118 	u16 ifs_clm_mntr_time;
5119 	enum rtw89_ifs_clm_application ifs_clm_app;
5120 	u16 ccx_period;
5121 	u8 ccx_unit_idx;
5122 	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5123 	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5124 	u16 ifs_clm_tx;
5125 	u16 ifs_clm_edcca_excl_cca;
5126 	u16 ifs_clm_ofdmfa;
5127 	u16 ifs_clm_ofdmcca_excl_fa;
5128 	u16 ifs_clm_cckfa;
5129 	u16 ifs_clm_cckcca_excl_fa;
5130 	u16 ifs_clm_total_ifs;
5131 	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5132 	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5133 	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5134 	u8 ifs_clm_tx_ratio;
5135 	u8 ifs_clm_edcca_excl_cca_ratio;
5136 	u8 ifs_clm_cck_fa_ratio;
5137 	u8 ifs_clm_ofdm_fa_ratio;
5138 	u8 ifs_clm_cck_cca_excl_fa_ratio;
5139 	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5140 	u16 ifs_clm_cck_fa_permil;
5141 	u16 ifs_clm_ofdm_fa_permil;
5142 	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5143 	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5144 };
5145 
5146 enum rtw89_ser_rcvy_step {
5147 	RTW89_SER_DRV_STOP_TX,
5148 	RTW89_SER_DRV_STOP_RX,
5149 	RTW89_SER_DRV_STOP_RUN,
5150 	RTW89_SER_HAL_STOP_DMA,
5151 	RTW89_SER_SUPPRESS_LOG,
5152 	RTW89_NUM_OF_SER_FLAGS
5153 };
5154 
5155 struct rtw89_ser {
5156 	u8 state;
5157 	u8 alarm_event;
5158 	bool prehandle_l1;
5159 
5160 	struct work_struct ser_hdl_work;
5161 	struct delayed_work ser_alarm_work;
5162 	const struct state_ent *st_tbl;
5163 	const struct event_ent *ev_tbl;
5164 	struct list_head msg_q;
5165 	spinlock_t msg_q_lock; /* lock when read/write ser msg */
5166 	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5167 };
5168 
5169 enum rtw89_mac_ax_ps_mode {
5170 	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5171 	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5172 	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
5173 	RTW89_MAC_AX_PS_MODE_MAX    = 3,
5174 };
5175 
5176 enum rtw89_last_rpwm_mode {
5177 	RTW89_LAST_RPWM_PS        = 0x0,
5178 	RTW89_LAST_RPWM_ACTIVE    = 0x6,
5179 };
5180 
5181 struct rtw89_lps_parm {
5182 	u8 macid;
5183 	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5184 	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5185 };
5186 
5187 struct rtw89_ppdu_sts_info {
5188 	struct sk_buff_head rx_queue[RTW89_PHY_MAX];
5189 	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
5190 };
5191 
5192 struct rtw89_early_h2c {
5193 	struct list_head list;
5194 	u8 *h2c;
5195 	u16 h2c_len;
5196 };
5197 
5198 struct rtw89_hw_scan_info {
5199 	struct ieee80211_vif *scanning_vif;
5200 	struct list_head pkt_list[NUM_NL80211_BANDS];
5201 	struct rtw89_chan op_chan;
5202 	bool abort;
5203 	u32 last_chan_idx;
5204 };
5205 
5206 enum rtw89_phy_bb_gain_band {
5207 	RTW89_BB_GAIN_BAND_2G = 0,
5208 	RTW89_BB_GAIN_BAND_5G_L = 1,
5209 	RTW89_BB_GAIN_BAND_5G_M = 2,
5210 	RTW89_BB_GAIN_BAND_5G_H = 3,
5211 	RTW89_BB_GAIN_BAND_6G_L = 4,
5212 	RTW89_BB_GAIN_BAND_6G_M = 5,
5213 	RTW89_BB_GAIN_BAND_6G_H = 6,
5214 	RTW89_BB_GAIN_BAND_6G_UH = 7,
5215 
5216 	RTW89_BB_GAIN_BAND_NR,
5217 };
5218 
5219 enum rtw89_phy_gain_band_be {
5220 	RTW89_BB_GAIN_BAND_2G_BE = 0,
5221 	RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5222 	RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5223 	RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5224 	RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5225 	RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5226 	RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5227 	RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5228 	RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5229 	RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5230 	RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5231 	RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5232 
5233 	RTW89_BB_GAIN_BAND_NR_BE,
5234 };
5235 
5236 enum rtw89_phy_bb_bw_be {
5237 	RTW89_BB_BW_20_40 = 0,
5238 	RTW89_BB_BW_80_160_320 = 1,
5239 
5240 	RTW89_BB_BW_NR_BE,
5241 };
5242 
5243 enum rtw89_bw20_sc {
5244 	RTW89_BW20_SC_20M = 1,
5245 	RTW89_BW20_SC_40M = 2,
5246 	RTW89_BW20_SC_80M = 4,
5247 	RTW89_BW20_SC_160M = 8,
5248 	RTW89_BW20_SC_320M = 16,
5249 };
5250 
5251 enum rtw89_cmac_table_bw {
5252 	RTW89_CMAC_BW_20M = 0,
5253 	RTW89_CMAC_BW_40M = 1,
5254 	RTW89_CMAC_BW_80M = 2,
5255 	RTW89_CMAC_BW_160M = 3,
5256 	RTW89_CMAC_BW_320M = 4,
5257 
5258 	RTW89_CMAC_BW_NR,
5259 };
5260 
5261 enum rtw89_phy_bb_rxsc_num {
5262 	RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5263 	RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5264 	RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5265 };
5266 
5267 struct rtw89_phy_bb_gain_info {
5268 	s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5269 	s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5270 	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5271 	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5272 	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5273 			[LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5274 	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5275 	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5276 		      [RTW89_BB_RXSC_NUM_40];
5277 	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5278 		      [RTW89_BB_RXSC_NUM_80];
5279 	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5280 		       [RTW89_BB_RXSC_NUM_160];
5281 };
5282 
5283 struct rtw89_phy_bb_gain_info_be {
5284 	s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5285 		   [LNA_GAIN_NUM];
5286 	s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5287 		   [TIA_GAIN_NUM];
5288 	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5289 			  [RF_PATH_MAX][LNA_GAIN_NUM];
5290 	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5291 		    [RF_PATH_MAX][LNA_GAIN_NUM];
5292 	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5293 			[RF_PATH_MAX][LNA_GAIN_NUM + 1];
5294 	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5295 		      [RTW89_BW20_SC_20M];
5296 	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5297 		      [RTW89_BW20_SC_40M];
5298 	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5299 		      [RTW89_BW20_SC_80M];
5300 	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5301 		       [RTW89_BW20_SC_160M];
5302 };
5303 
5304 struct rtw89_phy_efuse_gain {
5305 	bool offset_valid;
5306 	bool comp_valid;
5307 	s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5308 	s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
5309 	s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
5310 	s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5311 };
5312 
5313 #define RTW89_MAX_PATTERN_NUM             18
5314 #define RTW89_MAX_PATTERN_MASK_SIZE       4
5315 #define RTW89_MAX_PATTERN_SIZE            128
5316 
5317 struct rtw89_wow_cam_info {
5318 	bool r_w;
5319 	u8 idx;
5320 	u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5321 	u16 crc;
5322 	bool negative_pattern_match;
5323 	bool skip_mac_hdr;
5324 	bool uc;
5325 	bool mc;
5326 	bool bc;
5327 	bool valid;
5328 };
5329 
5330 struct rtw89_wow_key_info {
5331 	u8 ptk_tx_iv[8];
5332 	u8 valid_check;
5333 	u8 symbol_check_en;
5334 	u8 gtk_keyidx;
5335 	u8 rsvd[5];
5336 	u8 ptk_rx_iv[8];
5337 	u8 gtk_rx_iv[4][8];
5338 } __packed;
5339 
5340 struct rtw89_wow_gtk_info {
5341 	u8 kck[32];
5342 	u8 kek[32];
5343 	u8 tk1[16];
5344 	u8 txmickey[8];
5345 	u8 rxmickey[8];
5346 	__le32 igtk_keyid;
5347 	__le64 ipn;
5348 	u8 igtk[2][32];
5349 	u8 psk[32];
5350 } __packed;
5351 
5352 struct rtw89_wow_aoac_report {
5353 	u8 rpt_ver;
5354 	u8 sec_type;
5355 	u8 key_idx;
5356 	u8 pattern_idx;
5357 	u8 rekey_ok;
5358 	u8 ptk_tx_iv[8];
5359 	u8 eapol_key_replay_count[8];
5360 	u8 gtk[32];
5361 	u8 ptk_rx_iv[8];
5362 	u8 gtk_rx_iv[4][8];
5363 	u64 igtk_key_id;
5364 	u64 igtk_ipn;
5365 	u8 igtk[32];
5366 	u8 csa_pri_ch;
5367 	u8 csa_bw;
5368 	u8 csa_ch_offset;
5369 	u8 csa_chsw_failed;
5370 	u8 csa_ch_band;
5371 };
5372 
5373 struct rtw89_wow_param {
5374 	struct ieee80211_vif *wow_vif;
5375 	DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5376 	struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5377 	struct rtw89_wow_key_info key_info;
5378 	struct rtw89_wow_gtk_info gtk_info;
5379 	struct rtw89_wow_aoac_report aoac_rpt;
5380 	u8 pattern_cnt;
5381 	u8 ptk_alg;
5382 	u8 gtk_alg;
5383 	u8 ptk_keyidx;
5384 	u8 akm;
5385 
5386 	/* see RTW89_WOW_WAIT_COND series for wait condition */
5387 	struct rtw89_wait_info wait;
5388 
5389 	bool pno_inited;
5390 	struct list_head pno_pkt_list;
5391 	struct cfg80211_sched_scan_request *nd_config;
5392 };
5393 
5394 struct rtw89_mcc_limit {
5395 	bool enable;
5396 	u16 max_tob; /* TU; max time offset behind */
5397 	u16 max_toa; /* TU; max time offset ahead */
5398 	u16 max_dur; /* TU */
5399 };
5400 
5401 struct rtw89_mcc_policy {
5402 	u8 c2h_rpt;
5403 	u8 tx_null_early;
5404 	u8 dis_tx_null;
5405 	u8 in_curr_ch;
5406 	u8 dis_sw_retry;
5407 	u8 sw_retry_count;
5408 };
5409 
5410 struct rtw89_mcc_role {
5411 	struct rtw89_vif *rtwvif;
5412 	struct rtw89_mcc_policy policy;
5413 	struct rtw89_mcc_limit limit;
5414 
5415 	/* only valid when running with FW MRC mechanism */
5416 	u8 slot_idx;
5417 
5418 	/* byte-array in LE order for FW */
5419 	u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5420 
5421 	u16 duration; /* TU */
5422 	u16 beacon_interval; /* TU */
5423 	bool is_2ghz;
5424 	bool is_go;
5425 	bool is_gc;
5426 };
5427 
5428 struct rtw89_mcc_bt_role {
5429 	u16 duration; /* TU */
5430 };
5431 
5432 struct rtw89_mcc_courtesy {
5433 	bool enable;
5434 	u8 slot_num;
5435 	u8 macid_src;
5436 	u8 macid_tgt;
5437 };
5438 
5439 enum rtw89_mcc_plan {
5440 	RTW89_MCC_PLAN_TAIL_BT,
5441 	RTW89_MCC_PLAN_MID_BT,
5442 	RTW89_MCC_PLAN_NO_BT,
5443 
5444 	NUM_OF_RTW89_MCC_PLAN,
5445 };
5446 
5447 struct rtw89_mcc_pattern {
5448 	s16 tob_ref; /* TU; time offset behind of reference role */
5449 	s16 toa_ref; /* TU; time offset ahead of reference role */
5450 	s16 tob_aux; /* TU; time offset behind of auxiliary role */
5451 	s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5452 
5453 	enum rtw89_mcc_plan plan;
5454 	struct rtw89_mcc_courtesy courtesy;
5455 };
5456 
5457 struct rtw89_mcc_sync {
5458 	bool enable;
5459 	u16 offset; /* TU */
5460 	u8 macid_src;
5461 	u8 band_src;
5462 	u8 port_src;
5463 	u8 macid_tgt;
5464 	u8 band_tgt;
5465 	u8 port_tgt;
5466 };
5467 
5468 struct rtw89_mcc_config {
5469 	struct rtw89_mcc_pattern pattern;
5470 	struct rtw89_mcc_sync sync;
5471 	u64 start_tsf;
5472 	u16 mcc_interval; /* TU */
5473 	u16 beacon_offset; /* TU */
5474 };
5475 
5476 enum rtw89_mcc_mode {
5477 	RTW89_MCC_MODE_GO_STA,
5478 	RTW89_MCC_MODE_GC_STA,
5479 };
5480 
5481 struct rtw89_mcc_info {
5482 	struct rtw89_wait_info wait;
5483 
5484 	u8 group;
5485 	enum rtw89_mcc_mode mode;
5486 	struct rtw89_mcc_role role_ref; /* reference role */
5487 	struct rtw89_mcc_role role_aux; /* auxiliary role */
5488 	struct rtw89_mcc_bt_role bt_role;
5489 	struct rtw89_mcc_config config;
5490 };
5491 
5492 struct rtw89_dev {
5493 	struct ieee80211_hw *hw;
5494 	struct device *dev;
5495 	const struct ieee80211_ops *ops;
5496 
5497 	bool dbcc_en;
5498 	bool support_mlo;
5499 	enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5500 	struct rtw89_hw_scan_info scan_info;
5501 	const struct rtw89_chip_info *chip;
5502 	const struct rtw89_pci_info *pci_info;
5503 	const struct rtw89_rfe_parms *rfe_parms;
5504 	struct rtw89_hal hal;
5505 	struct rtw89_mcc_info mcc;
5506 	struct rtw89_mac_info mac;
5507 	struct rtw89_fw_info fw;
5508 	struct rtw89_hci_info hci;
5509 	struct rtw89_efuse efuse;
5510 	struct rtw89_traffic_stats stats;
5511 	struct rtw89_rfe_data *rfe_data;
5512 
5513 	/* ensures exclusive access from mac80211 callbacks */
5514 	struct mutex mutex;
5515 	struct list_head rtwvifs_list;
5516 	/* used to protect rf read write */
5517 	struct mutex rf_mutex;
5518 	struct workqueue_struct *txq_wq;
5519 	struct work_struct txq_work;
5520 	struct delayed_work txq_reinvoke_work;
5521 	/* used to protect ba_list and forbid_ba_list */
5522 	spinlock_t ba_lock;
5523 	/* txqs to setup ba session */
5524 	struct list_head ba_list;
5525 	/* txqs to forbid ba session */
5526 	struct list_head forbid_ba_list;
5527 	struct work_struct ba_work;
5528 	/* used to protect rpwm */
5529 	spinlock_t rpwm_lock;
5530 
5531 	struct rtw89_cam_info cam_info;
5532 
5533 	struct sk_buff_head c2h_queue;
5534 	struct work_struct c2h_work;
5535 	struct work_struct ips_work;
5536 	struct work_struct load_firmware_work;
5537 	struct work_struct cancel_6ghz_probe_work;
5538 
5539 	struct list_head early_h2c_list;
5540 
5541 	struct rtw89_ser ser;
5542 
5543 	DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5544 	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5545 	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5546 	DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5547 	DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5548 
5549 	struct rtw89_phy_stat phystat;
5550 	struct rtw89_rfk_wait_info rfk_wait;
5551 	struct rtw89_dack_info dack;
5552 	struct rtw89_iqk_info iqk;
5553 	struct rtw89_dpk_info dpk;
5554 	struct rtw89_rfk_mcc_info rfk_mcc;
5555 	struct rtw89_lck_info lck;
5556 	struct rtw89_rx_dck_info rx_dck;
5557 	bool is_tssi_mode[RF_PATH_MAX];
5558 	bool is_bt_iqk_timeout;
5559 
5560 	struct rtw89_fem_info fem;
5561 	struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5562 	struct rtw89_tssi_info tssi;
5563 	struct rtw89_power_trim_info pwr_trim;
5564 
5565 	struct rtw89_cfo_tracking_info cfo_tracking;
5566 	struct rtw89_env_monitor_info env_monitor;
5567 	struct rtw89_dig_info dig;
5568 	struct rtw89_phy_ch_info ch_info;
5569 	union {
5570 		struct rtw89_phy_bb_gain_info ax;
5571 		struct rtw89_phy_bb_gain_info_be be;
5572 	} bb_gain;
5573 	struct rtw89_phy_efuse_gain efuse_gain;
5574 	struct rtw89_phy_ul_tb_info ul_tb_info;
5575 	struct rtw89_antdiv_info antdiv;
5576 
5577 	struct delayed_work track_work;
5578 	struct delayed_work chanctx_work;
5579 	struct delayed_work coex_act1_work;
5580 	struct delayed_work coex_bt_devinfo_work;
5581 	struct delayed_work coex_rfk_chk_work;
5582 	struct delayed_work cfo_track_work;
5583 	struct delayed_work forbid_ba_work;
5584 	struct delayed_work roc_work;
5585 	struct delayed_work antdiv_work;
5586 	struct rtw89_ppdu_sts_info ppdu_sts;
5587 	u8 total_sta_assoc;
5588 	bool scanning;
5589 
5590 	struct rtw89_regulatory_info regulatory;
5591 	struct rtw89_sar_info sar;
5592 	struct rtw89_tas_info tas;
5593 
5594 	struct rtw89_btc btc;
5595 	enum rtw89_ps_mode ps_mode;
5596 	bool lps_enabled;
5597 
5598 	struct rtw89_wow_param wow;
5599 
5600 	/* napi structure */
5601 	struct net_device *netdev;
5602 	struct napi_struct napi;
5603 	int napi_budget_countdown;
5604 
5605 	struct rtw89_debugfs *debugfs;
5606 
5607 	/* HCI related data, keep last */
5608 	u8 priv[] __aligned(sizeof(void *));
5609 };
5610 
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)5611 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
5612 				     struct rtw89_core_tx_request *tx_req)
5613 {
5614 	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
5615 }
5616 
rtw89_hci_reset(struct rtw89_dev * rtwdev)5617 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
5618 {
5619 	rtwdev->hci.ops->reset(rtwdev);
5620 }
5621 
rtw89_hci_start(struct rtw89_dev * rtwdev)5622 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
5623 {
5624 	return rtwdev->hci.ops->start(rtwdev);
5625 }
5626 
rtw89_hci_stop(struct rtw89_dev * rtwdev)5627 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
5628 {
5629 	rtwdev->hci.ops->stop(rtwdev);
5630 }
5631 
rtw89_hci_deinit(struct rtw89_dev * rtwdev)5632 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
5633 {
5634 	return rtwdev->hci.ops->deinit(rtwdev);
5635 }
5636 
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)5637 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
5638 {
5639 	rtwdev->hci.ops->pause(rtwdev, pause);
5640 }
5641 
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)5642 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
5643 {
5644 	rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5645 }
5646 
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)5647 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5648 {
5649 	rtwdev->hci.ops->recalc_int_mit(rtwdev);
5650 }
5651 
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)5652 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5653 {
5654 	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5655 }
5656 
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)5657 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5658 {
5659 	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5660 }
5661 
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)5662 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5663 {
5664 	return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5665 }
5666 
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)5667 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5668 					  bool drop)
5669 {
5670 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5671 		return;
5672 
5673 	if (rtwdev->hci.ops->flush_queues)
5674 		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5675 }
5676 
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)5677 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5678 {
5679 	if (rtwdev->hci.ops->recovery_start)
5680 		rtwdev->hci.ops->recovery_start(rtwdev);
5681 }
5682 
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)5683 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5684 {
5685 	if (rtwdev->hci.ops->recovery_complete)
5686 		rtwdev->hci.ops->recovery_complete(rtwdev);
5687 }
5688 
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)5689 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5690 {
5691 	if (rtwdev->hci.ops->enable_intr)
5692 		rtwdev->hci.ops->enable_intr(rtwdev);
5693 }
5694 
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)5695 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5696 {
5697 	if (rtwdev->hci.ops->disable_intr)
5698 		rtwdev->hci.ops->disable_intr(rtwdev);
5699 }
5700 
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)5701 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5702 {
5703 	if (rtwdev->hci.ops->ctrl_txdma_ch)
5704 		rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5705 }
5706 
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)5707 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5708 {
5709 	if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5710 		rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5711 }
5712 
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)5713 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5714 {
5715 	if (rtwdev->hci.ops->ctrl_trxhci)
5716 		rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5717 }
5718 
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)5719 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
5720 {
5721 	int ret = 0;
5722 
5723 	if (rtwdev->hci.ops->poll_txdma_ch_idle)
5724 		ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
5725 	return ret;
5726 }
5727 
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)5728 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5729 {
5730 	if (rtwdev->hci.ops->clr_idx_all)
5731 		rtwdev->hci.ops->clr_idx_all(rtwdev);
5732 }
5733 
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)5734 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5735 {
5736 	int ret = 0;
5737 
5738 	if (rtwdev->hci.ops->rst_bdram)
5739 		ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5740 	return ret;
5741 }
5742 
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)5743 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5744 {
5745 	if (rtwdev->hci.ops->clear)
5746 		rtwdev->hci.ops->clear(rtwdev, pdev);
5747 }
5748 
5749 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)5750 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5751 {
5752 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5753 
5754 	return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5755 }
5756 
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)5757 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5758 {
5759 	return rtwdev->hci.ops->read8(rtwdev, addr);
5760 }
5761 
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)5762 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5763 {
5764 	return rtwdev->hci.ops->read16(rtwdev, addr);
5765 }
5766 
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)5767 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5768 {
5769 	return rtwdev->hci.ops->read32(rtwdev, addr);
5770 }
5771 
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)5772 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5773 {
5774 	rtwdev->hci.ops->write8(rtwdev, addr, data);
5775 }
5776 
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)5777 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5778 {
5779 	rtwdev->hci.ops->write16(rtwdev, addr, data);
5780 }
5781 
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)5782 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5783 {
5784 	rtwdev->hci.ops->write32(rtwdev, addr, data);
5785 }
5786 
5787 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5788 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5789 {
5790 	u8 val;
5791 
5792 	val = rtw89_read8(rtwdev, addr);
5793 	rtw89_write8(rtwdev, addr, val | bit);
5794 }
5795 
5796 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5797 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5798 {
5799 	u16 val;
5800 
5801 	val = rtw89_read16(rtwdev, addr);
5802 	rtw89_write16(rtwdev, addr, val | bit);
5803 }
5804 
5805 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5806 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5807 {
5808 	u32 val;
5809 
5810 	val = rtw89_read32(rtwdev, addr);
5811 	rtw89_write32(rtwdev, addr, val | bit);
5812 }
5813 
5814 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5815 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5816 {
5817 	u8 val;
5818 
5819 	val = rtw89_read8(rtwdev, addr);
5820 	rtw89_write8(rtwdev, addr, val & ~bit);
5821 }
5822 
5823 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5824 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5825 {
5826 	u16 val;
5827 
5828 	val = rtw89_read16(rtwdev, addr);
5829 	rtw89_write16(rtwdev, addr, val & ~bit);
5830 }
5831 
5832 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5833 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5834 {
5835 	u32 val;
5836 
5837 	val = rtw89_read32(rtwdev, addr);
5838 	rtw89_write32(rtwdev, addr, val & ~bit);
5839 }
5840 
5841 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5842 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5843 {
5844 	u32 shift = __ffs(mask);
5845 	u32 orig;
5846 	u32 ret;
5847 
5848 	orig = rtw89_read32(rtwdev, addr);
5849 	ret = (orig & mask) >> shift;
5850 
5851 	return ret;
5852 }
5853 
5854 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5855 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5856 {
5857 	u32 shift = __ffs(mask);
5858 	u32 orig;
5859 	u32 ret;
5860 
5861 	orig = rtw89_read16(rtwdev, addr);
5862 	ret = (orig & mask) >> shift;
5863 
5864 	return ret;
5865 }
5866 
5867 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5868 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5869 {
5870 	u32 shift = __ffs(mask);
5871 	u32 orig;
5872 	u32 ret;
5873 
5874 	orig = rtw89_read8(rtwdev, addr);
5875 	ret = (orig & mask) >> shift;
5876 
5877 	return ret;
5878 }
5879 
5880 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)5881 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
5882 {
5883 	u32 shift = __ffs(mask);
5884 	u32 orig;
5885 	u32 set;
5886 
5887 	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
5888 
5889 	orig = rtw89_read32(rtwdev, addr);
5890 	set = (orig & ~mask) | ((data << shift) & mask);
5891 	rtw89_write32(rtwdev, addr, set);
5892 }
5893 
5894 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)5895 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
5896 {
5897 	u32 shift;
5898 	u16 orig, set;
5899 
5900 	mask &= 0xffff;
5901 	shift = __ffs(mask);
5902 
5903 	orig = rtw89_read16(rtwdev, addr);
5904 	set = (orig & ~mask) | ((data << shift) & mask);
5905 	rtw89_write16(rtwdev, addr, set);
5906 }
5907 
5908 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)5909 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
5910 {
5911 	u32 shift;
5912 	u8 orig, set;
5913 
5914 	mask &= 0xff;
5915 	shift = __ffs(mask);
5916 
5917 	orig = rtw89_read8(rtwdev, addr);
5918 	set = (orig & ~mask) | ((data << shift) & mask);
5919 	rtw89_write8(rtwdev, addr, set);
5920 }
5921 
5922 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)5923 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5924 	      u32 addr, u32 mask)
5925 {
5926 	u32 val;
5927 
5928 	mutex_lock(&rtwdev->rf_mutex);
5929 	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
5930 	mutex_unlock(&rtwdev->rf_mutex);
5931 
5932 	return val;
5933 }
5934 
5935 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)5936 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5937 	       u32 addr, u32 mask, u32 data)
5938 {
5939 	mutex_lock(&rtwdev->rf_mutex);
5940 	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
5941 	mutex_unlock(&rtwdev->rf_mutex);
5942 }
5943 
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)5944 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
5945 {
5946 	void *p = rtwtxq;
5947 
5948 	return container_of(p, struct ieee80211_txq, drv_priv);
5949 }
5950 
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)5951 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
5952 				       struct ieee80211_txq *txq)
5953 {
5954 	struct rtw89_txq *rtwtxq;
5955 
5956 	if (!txq)
5957 		return;
5958 
5959 	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5960 	INIT_LIST_HEAD(&rtwtxq->list);
5961 }
5962 
rtwvif_to_vif(struct rtw89_vif * rtwvif)5963 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
5964 {
5965 	void *p = rtwvif;
5966 
5967 	return container_of(p, struct ieee80211_vif, drv_priv);
5968 }
5969 
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)5970 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
5971 {
5972 	return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
5973 }
5974 
vif_to_rtwvif_safe(struct ieee80211_vif * vif)5975 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
5976 {
5977 	return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
5978 }
5979 
rtwsta_to_sta(struct rtw89_sta * rtwsta)5980 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
5981 {
5982 	void *p = rtwsta;
5983 
5984 	return container_of(p, struct ieee80211_sta, drv_priv);
5985 }
5986 
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)5987 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
5988 {
5989 	return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
5990 }
5991 
sta_to_rtwsta_safe(struct ieee80211_sta * sta)5992 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
5993 {
5994 	return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
5995 }
5996 
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)5997 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
5998 {
5999 	if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6000 		return RATE_INFO_BW_160;
6001 	else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6002 		return RATE_INFO_BW_80;
6003 	else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6004 		return RATE_INFO_BW_40;
6005 	else
6006 		return RATE_INFO_BW_20;
6007 }
6008 
6009 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)6010 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6011 {
6012 	switch (hw_band) {
6013 	default:
6014 	case RTW89_BAND_2G:
6015 		return NL80211_BAND_2GHZ;
6016 	case RTW89_BAND_5G:
6017 		return NL80211_BAND_5GHZ;
6018 	case RTW89_BAND_6G:
6019 		return NL80211_BAND_6GHZ;
6020 	}
6021 }
6022 
6023 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)6024 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6025 {
6026 	switch (nl_band) {
6027 	default:
6028 	case NL80211_BAND_2GHZ:
6029 		return RTW89_BAND_2G;
6030 	case NL80211_BAND_5GHZ:
6031 		return RTW89_BAND_5G;
6032 	case NL80211_BAND_6GHZ:
6033 		return RTW89_BAND_6G;
6034 	}
6035 }
6036 
6037 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)6038 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6039 {
6040 	switch (width) {
6041 	default:
6042 		WARN(1, "Not support bandwidth %d\n", width);
6043 		fallthrough;
6044 	case NL80211_CHAN_WIDTH_20_NOHT:
6045 	case NL80211_CHAN_WIDTH_20:
6046 		return RTW89_CHANNEL_WIDTH_20;
6047 	case NL80211_CHAN_WIDTH_40:
6048 		return RTW89_CHANNEL_WIDTH_40;
6049 	case NL80211_CHAN_WIDTH_80:
6050 		return RTW89_CHANNEL_WIDTH_80;
6051 	case NL80211_CHAN_WIDTH_160:
6052 		return RTW89_CHANNEL_WIDTH_160;
6053 	}
6054 }
6055 
6056 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)6057 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6058 {
6059 	switch (rua) {
6060 	default:
6061 		WARN(1, "Invalid RU allocation: %d\n", rua);
6062 		fallthrough;
6063 	case 0 ... 36:
6064 		return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6065 	case 37 ... 52:
6066 		return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6067 	case 53 ... 60:
6068 		return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6069 	case 61 ... 64:
6070 		return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6071 	case 65 ... 66:
6072 		return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6073 	case 67:
6074 		return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6075 	case 68:
6076 		return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6077 	}
6078 }
6079 
6080 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6081 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
6082 						   struct rtw89_sta *rtwsta)
6083 {
6084 	if (rtwsta) {
6085 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
6086 
6087 		if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6088 			return &rtwsta->addr_cam;
6089 	}
6090 	return &rtwvif->addr_cam;
6091 }
6092 
6093 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6094 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
6095 						     struct rtw89_sta *rtwsta)
6096 {
6097 	if (rtwsta) {
6098 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
6099 
6100 		if (sta->tdls)
6101 			return &rtwsta->bssid_cam;
6102 	}
6103 	return &rtwvif->bssid_cam;
6104 }
6105 
6106 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6107 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6108 				    struct rtw89_channel_help_params *p,
6109 				    const struct rtw89_chan *chan,
6110 				    enum rtw89_mac_idx mac_idx,
6111 				    enum rtw89_phy_idx phy_idx)
6112 {
6113 	rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6114 					    mac_idx, phy_idx);
6115 }
6116 
6117 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6118 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6119 				 struct rtw89_channel_help_params *p,
6120 				 const struct rtw89_chan *chan,
6121 				 enum rtw89_mac_idx mac_idx,
6122 				 enum rtw89_phy_idx phy_idx)
6123 {
6124 	rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6125 					    mac_idx, phy_idx);
6126 }
6127 
6128 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6129 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6130 						  enum rtw89_chanctx_idx idx)
6131 {
6132 	struct rtw89_hal *hal = &rtwdev->hal;
6133 	enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6134 
6135 	if (roc_idx == idx)
6136 		return &hal->roc_chandef;
6137 
6138 	return &hal->chanctx[idx].chandef;
6139 }
6140 
6141 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6142 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6143 					enum rtw89_chanctx_idx idx)
6144 {
6145 	struct rtw89_hal *hal = &rtwdev->hal;
6146 
6147 	return &hal->chanctx[idx].chan;
6148 }
6149 
6150 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6151 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6152 						enum rtw89_chanctx_idx idx)
6153 {
6154 	struct rtw89_hal *hal = &rtwdev->hal;
6155 
6156 	return &hal->chanctx[idx].rcd;
6157 }
6158 
6159 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)6160 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6161 {
6162 	struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
6163 	struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
6164 
6165 	if (rtwvif)
6166 		return rtw89_chan_get(rtwdev, rtwvif->chanctx_idx);
6167 	else
6168 		return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
6169 }
6170 
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)6171 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6172 {
6173 	const struct rtw89_chip_info *chip = rtwdev->chip;
6174 
6175 	if (chip->ops->fem_setup)
6176 		chip->ops->fem_setup(rtwdev);
6177 }
6178 
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)6179 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6180 {
6181 	const struct rtw89_chip_info *chip = rtwdev->chip;
6182 
6183 	if (chip->ops->rfe_gpio)
6184 		chip->ops->rfe_gpio(rtwdev);
6185 }
6186 
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)6187 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6188 {
6189 	const struct rtw89_chip_info *chip = rtwdev->chip;
6190 
6191 	if (chip->ops->rfk_hw_init)
6192 		chip->ops->rfk_hw_init(rtwdev);
6193 }
6194 
6195 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6196 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6197 {
6198 	const struct rtw89_chip_info *chip = rtwdev->chip;
6199 
6200 	if (chip->ops->bb_preinit)
6201 		chip->ops->bb_preinit(rtwdev, phy_idx);
6202 }
6203 
6204 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)6205 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6206 {
6207 	const struct rtw89_chip_info *chip = rtwdev->chip;
6208 
6209 	if (!chip->ops->bb_postinit)
6210 		return;
6211 
6212 	chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6213 
6214 	if (rtwdev->dbcc_en)
6215 		chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6216 }
6217 
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)6218 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6219 {
6220 	const struct rtw89_chip_info *chip = rtwdev->chip;
6221 
6222 	if (chip->ops->bb_sethw)
6223 		chip->ops->bb_sethw(rtwdev);
6224 }
6225 
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)6226 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6227 {
6228 	const struct rtw89_chip_info *chip = rtwdev->chip;
6229 
6230 	if (chip->ops->rfk_init)
6231 		chip->ops->rfk_init(rtwdev);
6232 }
6233 
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)6234 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6235 {
6236 	const struct rtw89_chip_info *chip = rtwdev->chip;
6237 
6238 	if (chip->ops->rfk_init_late)
6239 		chip->ops->rfk_init_late(rtwdev);
6240 }
6241 
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)6242 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
6243 					  struct rtw89_vif *rtwvif)
6244 {
6245 	const struct rtw89_chip_info *chip = rtwdev->chip;
6246 
6247 	if (chip->ops->rfk_channel)
6248 		chip->ops->rfk_channel(rtwdev, rtwvif);
6249 }
6250 
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)6251 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6252 					       enum rtw89_phy_idx phy_idx,
6253 					       const struct rtw89_chan *chan)
6254 {
6255 	const struct rtw89_chip_info *chip = rtwdev->chip;
6256 
6257 	if (chip->ops->rfk_band_changed)
6258 		chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
6259 }
6260 
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool start)6261 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
6262 				       struct rtw89_vif *rtwvif, bool start)
6263 {
6264 	const struct rtw89_chip_info *chip = rtwdev->chip;
6265 
6266 	if (chip->ops->rfk_scan)
6267 		chip->ops->rfk_scan(rtwdev, rtwvif, start);
6268 }
6269 
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)6270 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6271 {
6272 	const struct rtw89_chip_info *chip = rtwdev->chip;
6273 
6274 	if (chip->ops->rfk_track)
6275 		chip->ops->rfk_track(rtwdev);
6276 }
6277 
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)6278 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6279 {
6280 	const struct rtw89_chip_info *chip = rtwdev->chip;
6281 
6282 	if (chip->ops->set_txpwr_ctrl)
6283 		chip->ops->set_txpwr_ctrl(rtwdev,  RTW89_PHY_0);
6284 }
6285 
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)6286 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6287 {
6288 	const struct rtw89_chip_info *chip = rtwdev->chip;
6289 
6290 	if (chip->ops->power_trim)
6291 		chip->ops->power_trim(rtwdev);
6292 }
6293 
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6294 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
6295 					      enum rtw89_phy_idx phy_idx)
6296 {
6297 	const struct rtw89_chip_info *chip = rtwdev->chip;
6298 
6299 	if (chip->ops->init_txpwr_unit)
6300 		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
6301 }
6302 
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)6303 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
6304 					enum rtw89_rf_path rf_path)
6305 {
6306 	const struct rtw89_chip_info *chip = rtwdev->chip;
6307 
6308 	if (!chip->ops->get_thermal)
6309 		return 0x10;
6310 
6311 	return chip->ops->get_thermal(rtwdev, rf_path);
6312 }
6313 
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)6314 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
6315 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
6316 					 struct ieee80211_rx_status *status)
6317 {
6318 	const struct rtw89_chip_info *chip = rtwdev->chip;
6319 
6320 	if (chip->ops->query_ppdu)
6321 		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
6322 }
6323 
rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)6324 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
6325 						  struct rtw89_rx_phy_ppdu *phy_ppdu)
6326 {
6327 	const struct rtw89_chip_info *chip = rtwdev->chip;
6328 
6329 	if (chip->ops->convert_rpl_to_rssi)
6330 		chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
6331 }
6332 
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6333 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
6334 					 enum rtw89_phy_idx phy_idx)
6335 {
6336 	const struct rtw89_chip_info *chip = rtwdev->chip;
6337 
6338 	if (chip->ops->ctrl_nbtg_bt_tx)
6339 		chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
6340 }
6341 
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)6342 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
6343 {
6344 	const struct rtw89_chip_info *chip = rtwdev->chip;
6345 
6346 	if (chip->ops->cfg_txrx_path)
6347 		chip->ops->cfg_txrx_path(rtwdev);
6348 }
6349 
6350 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)6351 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6352 				       struct ieee80211_vif *vif)
6353 {
6354 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6355 	const struct rtw89_chip_info *chip = rtwdev->chip;
6356 
6357 	if (!vif->bss_conf.he_support || !vif->cfg.assoc)
6358 		return;
6359 
6360 	if (chip->ops->set_txpwr_ul_tb_offset)
6361 		chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
6362 }
6363 
rtw89_chip_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6364 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
6365 					       enum rtw89_phy_idx phy_idx)
6366 {
6367 	const struct rtw89_chip_info *chip = rtwdev->chip;
6368 
6369 	if (chip->ops->digital_pwr_comp)
6370 		chip->ops->digital_pwr_comp(rtwdev, phy_idx);
6371 }
6372 
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)6373 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
6374 					  const struct rtw89_txpwr_table *tbl)
6375 {
6376 	tbl->load(rtwdev, tbl);
6377 }
6378 
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)6379 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
6380 {
6381 	const struct rtw89_regd *regd = rtwdev->regulatory.regd;
6382 
6383 	return regd->txpwr_regd[band];
6384 }
6385 
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6386 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
6387 					enum rtw89_phy_idx phy_idx)
6388 {
6389 	const struct rtw89_chip_info *chip = rtwdev->chip;
6390 
6391 	if (chip->ops->ctrl_btg_bt_rx)
6392 		chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
6393 }
6394 
6395 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)6396 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
6397 			     struct rtw89_rx_desc_info *desc_info,
6398 			     u8 *data, u32 data_offset)
6399 {
6400 	const struct rtw89_chip_info *chip = rtwdev->chip;
6401 
6402 	chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
6403 }
6404 
6405 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6406 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
6407 			    struct rtw89_tx_desc_info *desc_info,
6408 			    void *txdesc)
6409 {
6410 	const struct rtw89_chip_info *chip = rtwdev->chip;
6411 
6412 	chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
6413 }
6414 
6415 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6416 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
6417 				  struct rtw89_tx_desc_info *desc_info,
6418 				  void *txdesc)
6419 {
6420 	const struct rtw89_chip_info *chip = rtwdev->chip;
6421 
6422 	chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
6423 }
6424 
6425 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)6426 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
6427 			    const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
6428 {
6429 	const struct rtw89_chip_info *chip = rtwdev->chip;
6430 
6431 	chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
6432 }
6433 
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)6434 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6435 {
6436 	const struct rtw89_chip_info *chip = rtwdev->chip;
6437 
6438 	chip->ops->cfg_ctrl_path(rtwdev, wl);
6439 }
6440 
6441 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)6442 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
6443 			   u32 *tx_en, enum rtw89_sch_tx_sel sel)
6444 {
6445 	const struct rtw89_chip_info *chip = rtwdev->chip;
6446 
6447 	return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
6448 }
6449 
6450 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)6451 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
6452 {
6453 	const struct rtw89_chip_info *chip = rtwdev->chip;
6454 
6455 	return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
6456 }
6457 
6458 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6459 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
6460 				struct rtw89_vif *rtwvif,
6461 				struct rtw89_sta *rtwsta)
6462 {
6463 	const struct rtw89_chip_info *chip = rtwdev->chip;
6464 
6465 	if (!chip->ops->h2c_dctl_sec_cam)
6466 		return 0;
6467 	return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
6468 }
6469 
get_hdr_bssid(struct ieee80211_hdr * hdr)6470 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6471 {
6472 	__le16 fc = hdr->frame_control;
6473 
6474 	if (ieee80211_has_tods(fc))
6475 		return hdr->addr1;
6476 	else if (ieee80211_has_fromds(fc))
6477 		return hdr->addr2;
6478 	else
6479 		return hdr->addr3;
6480 }
6481 
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)6482 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
6483 {
6484 	if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6485 	    (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
6486 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
6487 			IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
6488 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
6489 			IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
6490 		return true;
6491 	return false;
6492 }
6493 
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)6494 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
6495 						      enum rtw89_fw_type type)
6496 {
6497 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
6498 
6499 	switch (type) {
6500 	case RTW89_FW_WOWLAN:
6501 		return &fw_info->wowlan;
6502 	case RTW89_FW_LOGFMT:
6503 		return &fw_info->log.suit;
6504 	case RTW89_FW_BBMCU0:
6505 		return &fw_info->bbmcu0;
6506 	case RTW89_FW_BBMCU1:
6507 		return &fw_info->bbmcu1;
6508 	default:
6509 		break;
6510 	}
6511 
6512 	return &fw_info->normal;
6513 }
6514 
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)6515 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
6516 						     unsigned int length)
6517 {
6518 	struct sk_buff *skb;
6519 
6520 	if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
6521 		skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
6522 		if (!skb)
6523 			return NULL;
6524 
6525 		skb_reserve(skb, RTW89_RADIOTAP_ROOM);
6526 		return skb;
6527 	}
6528 
6529 	return dev_alloc_skb(length);
6530 }
6531 
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)6532 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
6533 					       struct rtw89_tx_skb_data *skb_data,
6534 					       bool tx_done)
6535 {
6536 	struct rtw89_tx_wait_info *wait;
6537 
6538 	rcu_read_lock();
6539 
6540 	wait = rcu_dereference(skb_data->wait);
6541 	if (!wait)
6542 		goto out;
6543 
6544 	wait->tx_done = tx_done;
6545 	complete(&wait->completion);
6546 
6547 out:
6548 	rcu_read_unlock();
6549 }
6550 
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)6551 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
6552 {
6553 	switch (rtwdev->mlo_dbcc_mode) {
6554 	case MLO_1_PLUS_1_1RF:
6555 	case MLO_1_PLUS_1_2RF:
6556 	case DBCC_LEGACY:
6557 		return true;
6558 	default:
6559 		return false;
6560 	}
6561 }
6562 
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)6563 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
6564 {
6565 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
6566 
6567 	if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
6568 		return true;
6569 
6570 	return false;
6571 }
6572 
6573 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6574 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
6575 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
6576 		 struct sk_buff *skb, bool fwdl);
6577 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
6578 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
6579 				    int qsel, unsigned int timeout);
6580 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
6581 			    struct rtw89_tx_desc_info *desc_info,
6582 			    void *txdesc);
6583 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
6584 			       struct rtw89_tx_desc_info *desc_info,
6585 			       void *txdesc);
6586 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
6587 			       struct rtw89_tx_desc_info *desc_info,
6588 			       void *txdesc);
6589 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
6590 				     struct rtw89_tx_desc_info *desc_info,
6591 				     void *txdesc);
6592 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
6593 				     struct rtw89_tx_desc_info *desc_info,
6594 				     void *txdesc);
6595 void rtw89_core_rx(struct rtw89_dev *rtwdev,
6596 		   struct rtw89_rx_desc_info *desc_info,
6597 		   struct sk_buff *skb);
6598 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
6599 			     struct rtw89_rx_desc_info *desc_info,
6600 			     u8 *data, u32 data_offset);
6601 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
6602 				struct rtw89_rx_desc_info *desc_info,
6603 				u8 *data, u32 data_offset);
6604 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
6605 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
6606 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
6607 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
6608 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
6609 		       struct ieee80211_vif *vif,
6610 		       struct ieee80211_sta *sta);
6611 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
6612 			 struct ieee80211_vif *vif,
6613 			 struct ieee80211_sta *sta);
6614 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
6615 			    struct ieee80211_vif *vif,
6616 			    struct ieee80211_sta *sta);
6617 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
6618 			      struct ieee80211_vif *vif,
6619 			      struct ieee80211_sta *sta);
6620 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
6621 			  struct ieee80211_vif *vif,
6622 			  struct ieee80211_sta *sta);
6623 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6624 			       struct ieee80211_sta *sta,
6625 			       struct cfg80211_tid_config *tid_config);
6626 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
6627 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
6628 int rtw89_core_init(struct rtw89_dev *rtwdev);
6629 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
6630 int rtw89_core_register(struct rtw89_dev *rtwdev);
6631 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
6632 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6633 					   u32 bus_data_size,
6634 					   const struct rtw89_chip_info *chip);
6635 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
6636 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
6637 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
6638 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
6639 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
6640 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
6641 			      struct rtw89_chan *chan);
6642 int rtw89_set_channel(struct rtw89_dev *rtwdev);
6643 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6644 		       struct rtw89_chan *chan);
6645 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
6646 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
6647 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
6648 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
6649 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6650 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
6651 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6652 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
6653 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
6654 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
6655 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
6656 int rtw89_regd_init(struct rtw89_dev *rtwdev,
6657 		    void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
6658 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
6659 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
6660 			      struct rtw89_traffic_stats *stats);
6661 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
6662 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6663 			 const struct rtw89_completion_data *data);
6664 int rtw89_core_start(struct rtw89_dev *rtwdev);
6665 void rtw89_core_stop(struct rtw89_dev *rtwdev);
6666 void rtw89_core_update_beacon_work(struct work_struct *work);
6667 void rtw89_roc_work(struct work_struct *work);
6668 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6669 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6670 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6671 			   const u8 *mac_addr, bool hw_scan);
6672 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6673 			      struct ieee80211_vif *vif, bool hw_scan);
6674 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6675 			  bool active);
6676 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
6677 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
6678 
6679 #endif
6680