Home
last modified time | relevance | path

Searched refs:rptr (Results 1 – 25 of 105) sorted by relevance

12345

/linux/drivers/media/platform/amphion/
H A Dvpu_rpc.c40 ptr2 = desc->rptr; in vpu_rpc_check_buffer_space()
42 ptr1 = desc->rptr; in vpu_rpc_check_buffer_space()
112 msgword = *(u32 *)(shared->msg_mem_vir + desc->rptr - desc->start); in vpu_rpc_check_msg()
126 u32 rptr; in vpu_rpc_receive_msg_buf() local
133 data = (u32 *)(shared->msg_mem_vir + desc->rptr - desc->start); in vpu_rpc_receive_msg_buf()
134 rptr = desc->rptr; in vpu_rpc_receive_msg_buf()
137 rptr += 4; in vpu_rpc_receive_msg_buf()
138 if (rptr >= desc->end) { in vpu_rpc_receive_msg_buf()
139 rptr = desc->start; in vpu_rpc_receive_msg_buf()
153 rptr += 4; in vpu_rpc_receive_msg_buf()
[all …]
H A Dvpu_dbg.c288 iface->cmd_desc->rptr); in vpu_dbg_core()
296 iface->msg_desc->rptr); in vpu_dbg_core()
308 u32 rptr; in vpu_dbg_fwlog() local
316 rptr = print_buf->read; in vpu_dbg_fwlog()
319 if (rptr == wptr) in vpu_dbg_fwlog()
321 else if (rptr < wptr) in vpu_dbg_fwlog()
322 length = wptr - rptr; in vpu_dbg_fwlog()
324 length = print_buf->bytes + wptr - rptr; in vpu_dbg_fwlog()
331 if (rptr + length >= print_buf->bytes) { in vpu_dbg_fwlog()
332 int num = print_buf->bytes - rptr; in vpu_dbg_fwlog()
[all …]
H A Dvpu_helpers.c237 u32 *rptr, u32 size, void *dst) in vpu_helper_copy_from_stream_buffer() argument
244 if (!stream_buffer || !rptr || !dst) in vpu_helper_copy_from_stream_buffer()
250 offset = *rptr; in vpu_helper_copy_from_stream_buffer()
265 *rptr = vpu_helper_step_walk(stream_buffer, offset, size); in vpu_helper_copy_from_stream_buffer()
347 if (desc.rptr > desc.wptr) in vpu_helper_get_free_space()
348 return desc.rptr - desc.wptr; in vpu_helper_get_free_space()
349 else if (desc.rptr < desc.wptr) in vpu_helper_get_free_space()
350 return (desc.end - desc.start + desc.rptr - desc.wptr); in vpu_helper_get_free_space()
362 if (desc.wptr > desc.rptr) in vpu_helper_get_used_space()
363 return desc.wptr - desc.rptr; in vpu_helper_get_used_space()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c52 ih->rptr = 0; in amdgpu_ih_ring_init()
162 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
167 wptr, ih->rptr); in amdgpu_ih_ring_write()
196 ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout); in amdgpu_ih_wait_on_checkpoint_process_ts()
220 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
225 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
227 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
235 if (wptr != ih->rptr) in amdgpu_ih_process()
257 u32 ring_index = ih->rptr >> 2; in amdgpu_ih_decode_iv_helper()
284 ih->rptr += 32; in amdgpu_ih_decode_iv_helper()
[all …]
H A Damdgpu_ih.h69 unsigned rptr; member
87 uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
95 #define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ argument
97 (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
111 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
H A Dtonga_ih.c88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
247 u32 ring_index = ih->rptr >> 2; in tonga_ih_decode_iv()
263 ih->rptr += 16; in tonga_ih_decode_iv()
279 *ih->rptr_cpu = ih->rptr; in tonga_ih_set_rptr()
280 WDOORBELL32(ih->doorbell_index, ih->rptr); in tonga_ih_set_rptr()
282 WREG32(mmIH_RB_RPTR, ih->rptr); in tonga_ih_set_rptr()
H A Dcik_ih.c92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
253 u32 ring_index = ih->rptr >> 2; in cik_ih_decode_iv()
269 ih->rptr += 16; in cik_ih_decode_iv()
283 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
H A Dsi_ih.c59 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
136 u32 ring_index = ih->rptr >> 2; in si_ih_decode_iv()
150 ih->rptr += 16; in si_ih_decode_iv()
156 WREG32(IH_RB_RPTR, ih->rptr); in si_ih_set_rptr()
H A Diceland_ih.c92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
243 u32 ring_index = ih->rptr >> 2; in iceland_ih_decode_iv()
259 ih->rptr += 16; in iceland_ih_decode_iv()
273 WREG32(mmIH_RB_RPTR, ih->rptr); in iceland_ih_set_rptr()
H A Dcz_ih.c92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
244 u32 ring_index = ih->rptr >> 2; in cz_ih_decode_iv()
260 ih->rptr += 16; in cz_ih_decode_iv()
274 WREG32(mmIH_RB_RPTR, ih->rptr); in cz_ih_set_rptr()
H A Dvega10_ih.c127 ih->rptr = 0; in vega10_ih_toggle_ring_interrupts()
368 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
369 ih->rptr = tmp; in vega10_ih_get_wptr()
403 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
404 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_irq_rearm()
428 *ih->rptr_cpu = ih->rptr; in vega10_ih_set_rptr()
429 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_set_rptr()
435 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega10_ih_set_rptr()
H A Dih_v7_0.c156 ih->rptr = 0; in ih_v7_0_toggle_ring_interrupts()
430 wptr, ih->rptr, tmp); in ih_v7_0_get_wptr()
431 ih->rptr = tmp; in ih_v7_0_get_wptr()
465 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v7_0_irq_rearm()
466 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_irq_rearm()
485 *ih->rptr_cpu = ih->rptr; in ih_v7_0_set_rptr()
486 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v7_0_set_rptr()
492 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v7_0_set_rptr()
H A Dnavi10_ih.c182 ih->rptr = 0; in navi10_ih_toggle_ring_interrupts()
438 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
439 ih->rptr = tmp; in navi10_ih_get_wptr()
473 if ((v < ih->ring_size) && (v != ih->rptr)) in navi10_ih_irq_rearm()
474 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_irq_rearm()
498 *ih->rptr_cpu = ih->rptr; in navi10_ih_set_rptr()
499 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_set_rptr()
505 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in navi10_ih_set_rptr()
H A Dvega20_ih.c163 ih->rptr = 0; in vega20_ih_toggle_ring_interrupts()
448 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in vega20_ih_get_wptr()
449 ih->rptr = tmp; in vega20_ih_get_wptr()
484 if ((v < ih->ring_size) && (v != ih->rptr)) in vega20_ih_irq_rearm()
485 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_irq_rearm()
509 *ih->rptr_cpu = ih->rptr; in vega20_ih_set_rptr()
510 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_set_rptr()
516 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega20_ih_set_rptr()
H A Dih_v6_0.c184 ih->rptr = 0; in ih_v6_0_toggle_ring_interrupts()
458 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
459 ih->rptr = tmp; in ih_v6_0_get_wptr()
493 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_0_irq_rearm()
494 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_irq_rearm()
515 *ih->rptr_cpu = ih->rptr; in ih_v6_0_set_rptr()
516 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_set_rptr()
522 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_0_set_rptr()
/linux/sound/pci/riptide/
H A Driptide.c798 union cmdret rptr = CMDRET_ZERO; in writearm() local
802 SEND_RMEM(cif, 0x02, addr, &rptr); in writearm()
803 rptr.retlongs[0] &= (~mask); in writearm()
807 SEND_WMEM(cif, 0x02, (rptr.retlongs[0] | data)); in writearm()
808 SEND_RMEM(cif, 0x02, addr, &rptr); in writearm()
809 if ((rptr.retlongs[0] & data) == data) { in writearm()
813 rptr.retlongs[0] &= ~mask; in writearm()
924 union cmdret rptr = CMDRET_ZERO; in setmixer() local
930 SEND_RDGV(cif, num, num, &rptr); in setmixer()
931 if (rptr.retwords[0] == lval && rptr.retwords[1] == rval) in setmixer()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_ring.c85 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_free_size() local
88 ring->ring_free_dw = rptr + (ring->ring_size / 4); in radeon_ring_free_size()
256 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_test_lockup() local
260 if (rptr != atomic_read(&ring->last_rptr)) { in radeon_ring_test_lockup()
472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
482 rptr = radeon_ring_get_rptr(rdev, ring); in radeon_debugfs_ring_info_show()
484 rptr, rptr); in radeon_debugfs_ring_info_show()
508 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; in radeon_debugfs_ring_info_show()
511 if (rptr == i) in radeon_debugfs_ring_info_show()
/linux/drivers/net/ethernet/tehuti/
H A Dtn40.c53 f->rptr = 0; in tn40_fifo_alloc()
297 size = f->m.wptr - f->m.rptr; in tn40_rx_receive()
302 rxdd = (struct tn40_rxd_desc *)(f->m.va + f->m.rptr); in tn40_rx_receive()
348 f->m.rptr += tmp_len; in tn40_rx_receive()
349 tmp_len = f->m.rptr - f->m.memsz; in tn40_rx_receive()
351 f->m.rptr = tmp_len; in tn40_rx_receive()
358 f->m.rptr, tmp_len); in tn40_rx_receive()
412 tn40_write_reg(priv, f->m.reg_rptr, f->m.rptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_receive()
468 tn40_do_tx_db_ptr_next(db, &db->rptr); in tn40_tx_db_inc_rptr()
491 d->rptr = d->start; in tn40_tx_db_init()
[all …]
H A Dtehuti.c170 f->rptr = 0; in bdx_fifo_init()
1210 size = f->m.wptr - f->m.rptr; in bdx_rx_receive()
1216 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); in bdx_rx_receive()
1231 f->m.rptr += tmp_len; in bdx_rx_receive()
1233 tmp_len = f->m.rptr - f->m.memsz; in bdx_rx_receive()
1235 f->m.rptr = tmp_len; in bdx_rx_receive()
1238 f->m.rptr, tmp_len); in bdx_rx_receive()
1291 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); in bdx_rx_receive()
1370 BDX_ASSERT(*pptr != db->rptr && /* expect either read */ in __bdx_tx_db_ptr_next()
1387 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ in bdx_tx_db_inc_rptr()
[all …]
/linux/drivers/crypto/ccp/
H A Dtee-dev.c220 u32 rptr; in tee_submit_cmd() local
232 rptr = ioread32(tee->io_regs + tee->vdata->ring_rptr_reg); in tee_submit_cmd()
237 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
242 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
252 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
255 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_srv.c773 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); in dmub_srv_sync_inbox1() local
776 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { in dmub_srv_sync_inbox1()
779 dmub->inbox1_rb.rptr = rptr; in dmub_srv_sync_inbox1()
799 dmub->inbox1_rb.rptr = 0; in dmub_srv_hw_reset()
801 dmub->outbox0_rb.rptr = 0; in dmub_srv_hw_reset()
803 dmub->outbox1_rb.rptr = 0; in dmub_srv_hw_reset()
819 if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || in dmub_srv_cmd_queue()
846 flush_rb.rptr = dmub->inbox1_last_wptr; in dmub_srv_cmd_execute()
912 uint32_t i, rptr; in dmub_srv_wait_for_idle() local
918 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); in dmub_srv_wait_for_idle()
[all …]
/linux/drivers/video/fbdev/
H A Dmaxinefb.c77 unsigned char *rptr; in maxinefb_ims332_read_register() local
80 rptr = regs + 0x80000 + (regno << 4); in maxinefb_ims332_read_register()
81 j = *((volatile unsigned short *) rptr); in maxinefb_ims332_read_register()
/linux/drivers/net/ppp/
H A Dppp_deflate.c46 static int z_compress(void *state, unsigned char *rptr,
185 static int z_compress(void *arg, unsigned char *rptr, unsigned char *obuf, in z_compress() argument
195 proto = PPP_PROTOCOL(rptr); in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
221 rptr += off; in z_compress()
222 state->strm.next_in = rptr; in z_compress()
/linux/drivers/gpu/drm/qxl/
H A Dqxl_object.c210 void *rptr; in qxl_bo_kmap_atomic_page() local
226 rptr = bo->kptr + (page_offset * PAGE_SIZE); in qxl_bo_kmap_atomic_page()
227 return rptr; in qxl_bo_kmap_atomic_page()
233 rptr = bo_map.vaddr; /* TODO: Use mapping abstraction properly */ in qxl_bo_kmap_atomic_page()
235 rptr += page_offset * PAGE_SIZE; in qxl_bo_kmap_atomic_page()
236 return rptr; in qxl_bo_kmap_atomic_page()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h5791 uint32_t rptr; /**< Read pointer for consumer in bytes */ member
5808 return (rb->wrpt == rb->rptr); in dmub_rb_empty()
5822 if (rb->wrpt >= rb->rptr) in dmub_rb_full()
5823 data_count = rb->wrpt - rb->rptr; in dmub_rb_full()
5825 data_count = rb->capacity - (rb->rptr - rb->wrpt); in dmub_rb_full()
5898 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_front()
5919 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; in dmub_rb_get_rptr_with_offset()
5936 uint32_t rptr) in dmub_rb_peek_offset() argument
5938 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; in dmub_rb_peek_offset()
5959 …nst uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); in dmub_rb_out_front()
[all …]

12345