Searched refs:rmmio (Results 1 – 9 of 9) sorted by relevance
1453 vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd; in amdgpu_virt_rlcg_vfi_reg_rw()1454 vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat; in amdgpu_virt_rlcg_vfi_reg_rw()1455 vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr; in amdgpu_virt_rlcg_vfi_reg_rw()1456 vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data; in amdgpu_virt_rlcg_vfi_reg_rw()1457 vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl; in amdgpu_virt_rlcg_vfi_reg_rw()1458 vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx; in amdgpu_virt_rlcg_vfi_reg_rw()1575 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()1576 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()1577 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()1578 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()[all …]
3917 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); in amdgpu_device_init()3918 if (!adev->rmmio) in amdgpu_device_init()4252 iounmap(adev->rmmio); in amdgpu_device_unmap_mmio()4253 adev->rmmio = NULL; in amdgpu_device_unmap_mmio()4380 if (adev->rmmio) { in amdgpu_device_fini_sw()4381 iounmap(adev->rmmio); in amdgpu_device_fini_sw()4382 adev->rmmio = NULL; in amdgpu_device_fini_sw()
668 void __iomem *rmmio; member
732 dev->rmmio = devm_ioremap(dev->drm.dev, in vmw_setup_pci_resources()735 if (!dev->rmmio) { in vmw_setup_pci_resources()
4133 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_rreg_slow()4134 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_rreg_slow()4144 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_wreg_slow()4145 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_wreg_slow()
2656 u32 val = readl(hdev->rmmio + reg); in hl_rreg()2679 writel(val, hdev->rmmio + reg); in hl_wreg()
517 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + in goya_pci_bars_map()
719 hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] + in gaudi_pci_bars_map()
2971 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + (CFG_BASE - STM_FLASH_BASE_ADDR); in gaudi2_pci_bars_map()