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Searched refs:rlc (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
H A Damdgpu_ucode.c887 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
888 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; in amdgpu_ucode_init_single_fw()
891 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
892 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; in amdgpu_ucode_init_single_fw()
895 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
896 ucode_addr = adev->gfx.rlc.save_restore_list_srm; in amdgpu_ucode_init_single_fw()
899 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
900 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; in amdgpu_ucode_init_single_fw()
903 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
904 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; in amdgpu_ucode_init_single_fw()
[all …]
H A Dgfx_v7_0.c2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3195 /* allocate rlc buffers */ in gfx_v7_0_rlc_init()
3198 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3199 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3202 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3203 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3207 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3208 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3209 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3211 src_ptr = adev->gfx.rlc in gfx_v7_0_rlc_init()
3283 gfx_v7_0_update_rlc(struct amdgpu_device * adev,u32 rlc) gfx_v7_0_update_rlc() argument
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H A Dgfx_v6_0.c2019 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2341 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2342 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2345 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2346 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2347 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2348 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2359 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2360 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2365 &adev->gfx.rlc.clear_state_obj, in gfx_v6_0_rlc_init()
[all …]
H A Dgfx_v8_0.c936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1054 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1056 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1058 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1060 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1062 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1064 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1066 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1068 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1070 adev->gfx.rlc in gfx_v8_0_init_microcode()
[all...]
H A Dsoc15_common.h41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
46 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
H A Dgfx_v9_0.c1263 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_check_fw_write_wait()
1407 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_init_cp_gfx_microcode()
1620 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_init_always_on_cu_mask()
1632 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_init_always_on_cu_mask()
1813 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_mec_init()
1821 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_0_mec_init()
1829 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_mec_init()
1831 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_mec_init()
1842 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_mec_init()
2272 if (adev->gfx.rlc in gfx_v9_0_sw_init()
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H A Dgfx_v12_0.c527 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
650 if (adev->gfx.rlc.cs_data == NULL) in gfx_v12_0_get_csb_buffer()
657 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v12_0_get_csb_buffer()
677 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v12_0_rlc_fini()
678 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v12_0_rlc_fini()
679 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v12_0_rlc_fini()
682 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v12_0_rlc_fini()
683 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v12_0_rlc_fini()
684 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v12_0_rlc_fini()
691 reg_access_ctrl = &adev->gfx.rlc in gfx_v12_0_init_rlcg_reg_access_ctrl()
[all...]
H A Dgfx_v11_0.c629 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_init_toc_microcode()
812 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
824 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
855 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_init_rlcg_reg_access_ctrl()
856 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_init_rlcg_reg_access_ctrl()
857 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_init_rlcg_reg_access_ctrl()
860 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_init_rlcg_reg_access_ctrl()
861 &adev->gfx.rlc.cp_table_gpu_addr,
862 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_init()
869 reg_access_ctrl = &adev->gfx.rlc in gfx_v11_0_rlc_init()
[all...]
H A Dgfx_v10_0.c4049 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4240 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4252 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4283 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4284 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4285 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4288 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4289 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4290 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4297 reg_access_ctrl = &adev->gfx.rlc in gfx_v10_0_init_rlcg_reg_access_ctrl()
[all...]
H A Dgfx_v9_4_3.c533 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_4_3_mec_init()
1108 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_4_3_xcc_constants_init()
1110 DRM_ERROR("Failed to init rlc BOs!\n"); in gfx_v9_4_3_xcc_constants_init()
1202 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1351 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v9_4_3_rlc_start()
1409 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_xcc_rlc_resume()
1418 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_4_3_rlc_resume()
1424 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v9_4_3_rlc_resume()
1425 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v9_4_3_rlc_resume()
1552 "Using rlc debu in gfx_v9_4_3_xcc_cp_compute_load_microcode()
[all...]
H A Daldebaran.c269 adev->gfx.rlc.funcs->resume(adev); in aldebaran_mode2_restore_ip()
H A Damdgpu_ucode.h433 struct rlc_firmware_header_v1_0 rlc; member
H A Damdgpu_virt.c1014 if (!adev->gfx.rlc.rlcg_reg_access_supported) { in amdgpu_virt_rlcg_reg_rw()
1028 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
H A Damdgpu_gfx.h362 struct amdgpu_rlc rlc;
351 struct amdgpu_rlc rlc; global() member
H A Damdgpu_device.c678 adev->gfx.rlc.rlcg_reg_access_supported && in amdgpu_device_xcc_rreg()
761 * @reg: mmio/rlc register
775 adev->gfx.rlc.funcs && in amdgpu_mm_wreg_mmio_rlc()
776 adev->gfx.rlc.funcs->is_rlcg_access_range) { in amdgpu_mm_wreg_mmio_rlc()
777 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) in amdgpu_mm_wreg_mmio_rlc()
809 adev->gfx.rlc.rlcg_reg_access_supported && in amdgpu_device_xcc_wreg()
/linux/drivers/gpu/drm/radeon/
H A Devergreen.c4026 /* halt the rlc */ in evergreen_gpu_pci_config_reset()
4114 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4115 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4118 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4119 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4121 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4126 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4127 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4130 radeon_bo_unpin(rdev->rlc in sumo_rlc_fini()
[all...]
H A Dradeon_ucode.h215 struct rlc_firmware_header_v1_0 rlc; member
H A Dcik.c4943 /* stop the rlc */ in cik_gpu_soft_reset()
5166 /* halt the rlc, disable cp internal ints */ in cik_gpu_pci_config_reset()
5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5811 if (tmp != rlc) in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6420 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6424 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6616 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc in cik_init_gfx_cgpg()
[all...]
H A Dsi.c3856 /* stop the rlc */ in si_gpu_soft_reset()
4040 /* halt the rlc, disable cp internal ints */ in si_gpu_pci_config_reset()
5201 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5206 if (tmp != rlc) in si_update_rlc()
5207 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5263 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5269 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5669 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5677 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5701 if (rdev->rlc in si_get_csb_buffer()
[all...]
H A Dni.c2162 /* allocate rlc buffers */ in cayman_startup()
2164 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2165 rdev->rlc.reg_list_size = in cayman_startup()
2167 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2170 DRM_ERROR("Failed to init rlc BOs!\n"); in cayman_startup()
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Dphy-ctxt.c185 iwl_mvm_phy_ctxt_set_rxchain(mvm, ctxt, &cmd.rlc.rx_chain_info, in iwl_mvm_phy_send_rlc()
189 ctxt->id, cmd.rlc.rx_chain_info); in iwl_mvm_phy_send_rlc()
/linux/arch/arc/lib/
H A Dstrcmp.S77 rlc r0,0 ; r0 := r2 > r3 ? 1 : 0
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Ddatapath.h469 struct iwl_rlc_properties rlc; member
/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-fwht.c55 rlc(const s16 *in, __be16 *output, int blocktype) in rlc() function
732 size = rlc(cf->coeffs, *rlco, blocktype); in encode_plane()

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