| /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| H A D | hclge_err.c | 12 .reset_level = HNAE3_NONE_RESET
16 .reset_level = HNAE3_NONE_RESET
20 .reset_level = HNAE3_NONE_RESET
24 .reset_level = HNAE3_NONE_RESET
28 .reset_level = HNAE3_NONE_RESET
32 .reset_level = HNAE3_NONE_RESET
36 .reset_level = HNAE3_NONE_RESET
40 .reset_level = HNAE3_NONE_RESET
44 .reset_level = HNAE3_NONE_RESET
54 .reset_level = HNAE3_NONE_RESET
[all …]
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| H A D | hclge_err.h | 201 enum hnae3_reset_type reset_level; member
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| H A D | hclge_main.c | 4268 enum hnae3_reset_type reset_level; in hclge_update_reset_level() local
4280 reset_level = hclge_get_reset_level(ae_dev, in hclge_update_reset_level()
4282 if (reset_level != HNAE3_NONE_RESET) in hclge_update_reset_level()
4283 set_bit(reset_level, &hdev->reset_request); in hclge_update_reset_level()
4466 hdev->reset_level = in hclge_reset_event()
4470 hdev->reset_level = HNAE3_FUNC_RESET; in hclge_reset_event()
4474 hdev->reset_level); in hclge_reset_event()
4477 set_bit(hdev->reset_level, &hdev->reset_request); in hclge_reset_event()
4480 if (hdev->reset_level < HNAE3_GLOBAL_RESET) in hclge_reset_event()
4481 hdev->reset_level++; in hclge_reset_event()
[all …]
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| H A D | hclge_main.h | 881 enum hnae3_reset_type reset_level; member
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| H A D | fw_reset.c | 85 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level, in mlx5_reg_mfrl_set() argument
91 MLX5_SET(mfrl_reg, in, reset_level, reset_level); in mlx5_reg_mfrl_set()
99 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level, in mlx5_reg_mfrl_query() argument
110 if (reset_level) in mlx5_reg_mfrl_query()
111 *reset_level = MLX5_GET(mfrl_reg, out, reset_level); in mlx5_reg_mfrl_query()
122 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type) in mlx5_fw_reset_query() argument
124 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL, NULL); in mlx5_fw_reset_query()
180 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3); in mlx5_fw_reset_set_reset_sync()
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| H A D | devlink.c | 90 u8 reset_level, reset_type, net_port_alive; in mlx5_devlink_reload_fw_activate() local
93 err = mlx5_fw_reset_query(dev, &reset_level, &reset_type); in mlx5_devlink_reload_fw_activate()
96 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL3)) { in mlx5_devlink_reload_fw_activate()
122 u8 reset_level; in mlx5_devlink_trigger_fw_live_patch() local
125 err = mlx5_fw_reset_query(dev, &reset_level, NULL); in mlx5_devlink_trigger_fw_live_patch()
128 if (!(reset_level & MLX5_MFRL_REG_RESET_LEVEL0)) { in mlx5_devlink_trigger_fw_live_patch()
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| H A D | fw_reset.h | 9 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type);
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_fw_update.h | 14 u8 *reset_level, struct netlink_ext_ack *extack);
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_client.c | 24 u32 reset_level);
631 u32 reset_level) in i40e_client_request_reset() argument
635 switch (reset_level) { in i40e_client_request_reset()
645 pf->hw.pf_id, reset_level); in i40e_client_request_reset()
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| /linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/ |
| H A D | hclgevf_main.h | 219 enum hnae3_reset_type reset_level; member
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| H A D | hclgevf_main.c | 1688 hdev->reset_level = in hclgevf_reset_event()
1691 hdev->reset_level = HNAE3_VF_FUNC_RESET; in hclgevf_reset_event()
1694 hdev->reset_level); in hclgevf_reset_event()
1883 hclgevf_set_reset_pending(hdev, hdev->reset_level); in hclgevf_reset_service_task()
2944 hdev->reset_level = HNAE3_VF_FUNC_RESET; in hclgevf_init_hdev()
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| /linux/drivers/soc/tegra/ |
| H A D | pmc.c | 2188 static DEVICE_ATTR_RO(reset_level);
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| /linux/include/linux/mlx5/ |
| H A D | mlx5_ifc.h | 11400 u8 reset_level[0x8]; member
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