| /linux/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-allocator.c | 37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
187 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
228 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
231 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
232 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
240 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
243 if (res_pool->hubbub) { in dcn201_init_hw()
244 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
246 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
248 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 91 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
137 struct abm **abms = dc->res_pool->multiple_abms; in dcn401_init_hw()
140 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
156 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
157 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
176 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn401_init_hw()
179 if (res_pool->hubbub) { in dcn401_init_hw()
180 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
182 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn401_init_hw()
184 current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn401_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
192 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
194 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
196 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
242 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
246 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
250 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
268 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
272 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
276 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 265 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
342 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
343 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
356 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
358 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
360 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
361 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
364 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
365 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
386 if (!dc->res_pool) in destroy_link_encoders()
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| H A D | dc_stream.c | 204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
318 if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { in dc_stream_check_cursor_attributes()
319 max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream); in dc_stream_check_cursor_attributes()
486 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
534 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
555 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
567 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
585 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
665 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
839 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { in dc_stream_add_dsc_to_resource()
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| H A D | dc_resource.c | 266 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
271 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
275 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
279 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
284 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
288 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
292 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
296 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
300 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
306 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_edp_panel_control.c | 588 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
589 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
636 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
637 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
733 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
734 psr = dc->res_pool->psr; in edp_setup_psr()
834 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
911 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
926 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
940 struct dmub_replay *replay = dc->res_pool->replay; in edp_set_replay_allow_active()
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| H A D | link_dp_capability.c | 285 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; in get_clock_source_id()
344 struct resource_pool *res_pool = link->dc->res_pool; in dp_is_fec_supported() local
345 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_is_fec_supported()
2243 struct resource_pool *res_pool = link->dc->res_pool; in dp_get_max_link_enc_cap() local
2244 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_get_max_link_enc_cap()
2282 struct resource_pool *res_pool = link->dc->res_pool; in dp_get_max_link_cap() local
2283 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_get_max_link_cap()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_factory.c | 397 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
398 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
555 if (link->dc->res_pool->funcs->link_init) in construct_phy()
556 link->dc->res_pool->funcs->link_init(link); in construct_phy()
677 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
691 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
692 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
696 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
703 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
867 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
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| H A D | link_detection.c | 209 &link->dc->res_pool->audio_support; in link_detect_sink_signal_type()
592 struct audio_support *audio_support = &link->dc->res_pool->audio_support; in detect_dp()
829 link->dc->res_pool->funcs->link_encs_assign && in should_verify_link_capability_destructively()
967 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in detect_link_and_local_sink()
1324 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) in detect_link_and_local_sink()
1325 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); in detect_link_and_local_sink()
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| H A D | link_resource.c | 84 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count; in link_restore_res_map()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 522 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 274 dc->res_pool->res_cap->num_timing_generator; in dcn351_update_bw_bounding_box_fpu()
275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn351_update_bw_bounding_box_fpu()
486 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
589 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_populate_dml_pipes_from_context_fpu()
616 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 240 dc->res_pool->res_cap->num_timing_generator; in dcn35_update_bw_bounding_box_fpu()
241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn35_update_bw_bounding_box_fpu()
453 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
556 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_populate_dml_pipes_from_context_fpu()
586 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn35_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/modules/power/ |
| H A D | power_helpers.c | 692 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
702 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
756 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
757 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
758 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
760 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
761 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); in dmub_init_abm_config()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 76 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
129 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 926 params[i].sink->ctx->dc->res_pool->dscs[0], in set_dsc_configs_from_fairness_vars()
979 param.sink->ctx->dc->res_pool->dscs[0], in bpp_x16_from_pbn()
1248 stream->sink->ctx->dc->res_pool->dscs[0], in compute_mst_dsc_configs_for_link()
1491 struct resource_pool *res_pool; in compute_mst_dsc_configs_for_state() local
1500 res_pool = stream->ctx->dc->res_pool; in compute_mst_dsc_configs_for_state()
1519 if (res_pool->funcs->remove_stream_from_ctx && in compute_mst_dsc_configs_for_state()
1520 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) in compute_mst_dsc_configs_for_state()
1785 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], in is_dsc_common_config_possible()
1946 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0], in dm_dp_mst_is_port_support_mode()
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