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Searched refs:res_pool (Results 1 – 25 of 43) sorted by relevance

12

/linux/drivers/bus/fsl-mc/
H A Dfsl-mc-allocator.c37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c92 struct dccg *dccg = dc->res_pool->dccg; in dcn50_update_dchubp_dpp()
264 struct dccg *dccg = dc->res_pool->dccg; in dcn50_update_dchubp_dpp_sequence()
422 struct mpc *mpc = dc->res_pool->mpc; in dcn50_update_mpcc_sequence()
533 struct abm **abms = dc->res_pool->multiple_abms; in dcn50_init_hw()
536 struct resource_pool *res_pool = dc->res_pool; in dcn50_init_hw() local
552 if (res_pool->dccg->funcs->dccg_init) in dcn50_init_hw()
553 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn50_init_hw()
572 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn50_init_hw()
575 if (res_pool->hubbub) { in dcn50_init_hw()
576 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn50_init_hw()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/
H A Ddcn60_hwseq.c345 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_setup_audio_dto()
361 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dcn60_setup_audio_dto()
369 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
370 dc->res_pool->dccg, in dcn60_setup_audio_dto()
374 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
375 dc->res_pool->dccg, in dcn60_setup_audio_dto()
395 if (i == dc->res_pool->pipe_count) { in dcn60_setup_audio_dto()
396 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn60_setup_audio_dto()
414 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dcn60_setup_audio_dto()
422 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( in dcn60_setup_audio_dto()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c80 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
448 ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count); in dcn30_set_writeback()
449 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
453 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
466 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
488 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
502 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
517 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
542 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
543 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
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/linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/
H A Ddcn42_pg_cntl.c42 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_status) in pg_cntl42_save_and_disable_global_fgcg_rep()
43 …obal_ono_rep_fgcg = pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_status(pg_cntl->… in pg_cntl42_save_and_disable_global_fgcg_rep()
47 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) in pg_cntl42_save_and_disable_global_fgcg_rep()
48 …pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg,… in pg_cntl42_save_and_disable_global_fgcg_rep()
59 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) in pg_cntl42_restore_global_fgcg_rep()
60 …pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg,… in pg_cntl42_restore_global_fgcg_rep()
522 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_plane_otg_pg_control()
554 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_plane_otg_pg_control()
581 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_init_pg_status()
591 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl42_init_pg_status()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c267 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
344 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
345 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
358 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
360 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
362 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
363 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
366 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
367 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
388 if (!dc->res_pool) in destroy_link_encoders()
[all …]
H A Ddc_resource.c279 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
284 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
288 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
292 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
297 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
301 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
305 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
309 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
313 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
319 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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H A Ddc_surface.c73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
151 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
331 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_edid_parser.c35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
/linux/drivers/gpu/drm/amd/display/modules/power/
H A Dpower_abm.c871 dmcu = dc->res_pool->dmcu; in mod_power_hw_init_backlight()
880 if (!dmub_init_abm_config(dc->res_pool, params, i)) in mod_power_hw_init_backlight()
1662 if (!dmub_is_abm_supported(dc->res_pool, inst)) in mod_power_is_abm_supported()
1686 if (!dmub_set_abm_event(dc->res_pool, full_screen, trans_info, in mod_power_abm_set_event()
1710 if (!dmub_set_abm_strength(dc->res_pool, strength, inst)) in mod_power_abm_set_strength()
2178 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
2188 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
2245 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
2246 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
2247 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
[all …]
H A Dpower.c195 if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23)) in mod_power_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/
H A Ddcn42_dccg.c282 struct resource_pool *res_pool = dccg->ctx->dc->res_pool; in dccg42_init() local
288 for (i = 0; i < res_pool->hpo_dp_stream_enc_count; i++) in dccg42_init()
292 for (i = 0; i < res_pool->hpo_dp_link_enc_count; i++) in dccg42_init()
297 for (i = 0; i < res_pool->hpo_dp_stream_enc_count; i++) in dccg42_init()
306 for (i = 0; i < res_pool->pipe_count; i++) { in dccg42_init()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c585 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
586 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
633 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
634 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
730 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
731 psr = dc->res_pool->psr; in edp_setup_psr()
831 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
909 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
924 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
938 struct dmub_replay *replay = dc->res_pool->replay; in edp_set_replay_allow_active()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_factory.c423 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
424 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
595 if (link->dc->res_pool->funcs->link_init) in construct_phy()
596 link->dc->res_pool->funcs->link_init(link); in construct_phy()
658 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
773 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
774 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
778 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
785 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
874 (link->dc->res_pool->funcs->hpo_frl_link_enc_create)) { in construct_phy()
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H A Dlink_dpms.c140 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { in link_blank_dp_stream()
141 if (fe == dc->res_pool->stream_enc[j]->id) { in link_blank_dp_stream()
142 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, in link_blank_dp_stream()
143 dc->res_pool->stream_enc[j]); in link_blank_dp_stream()
734 struct dccg *dccg = dc->res_pool->dccg; in link_set_dsc_on_stream()
1948 (!core_dc->res_pool->dccg->funcs->enable_hdmicharclk) || in enable_link_hdmi_frl()
2001 if (core_dc->res_pool->dccg->funcs->set_valid_pixel_rate) in enable_link_hdmi_frl()
2002 core_dc->res_pool->dccg->funcs->set_valid_pixel_rate( in enable_link_hdmi_frl()
2003 core_dc->res_pool->dccg, in enable_link_hdmi_frl()
2020 if (core_dc->res_pool->dccg->funcs->set_hdmistreamclk) { in enable_link_hdmi_frl()
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H A Dlink_resource.c84 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count; in link_restore_res_map()
H A Dlink_detection.c204 aud_support = &link->dc->res_pool->audio_support; in link_detect_sink_signal_type()
626 struct audio_support *audio_support = &link->dc->res_pool->audio_support; in detect_dp()
956 link->dc->res_pool->funcs->link_encs_assign && in should_verify_link_capability_destructively()
1109 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in detect_link_and_local_sink()
1498 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) in detect_link_and_local_sink()
1499 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); in detect_link_and_local_sink()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/
H A Damdgpu_dm_crtc_test.c503 struct resource_pool *res_pool; in dm_test_crtc_set_vupdate_irq_enable() local
517 res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL); in dm_test_crtc_set_vupdate_irq_enable()
518 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, res_pool); in dm_test_crtc_set_vupdate_irq_enable()
532 res_pool->irqs = irqs; in dm_test_crtc_set_vupdate_irq_enable()
533 dc->res_pool = res_pool; in dm_test_crtc_set_vupdate_irq_enable()
1004 struct resource_pool *res_pool; in dm_test_crtc_enable_vblank_vupdate_busy() local
1018 res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL); in dm_test_crtc_enable_vblank_vupdate_busy()
1019 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, res_pool); in dm_test_crtc_enable_vblank_vupdate_busy()
1033 res_pool->irqs = irqs; in dm_test_crtc_enable_vblank_vupdate_busy()
1034 adev->dm.dc->res_pool = res_pool; in dm_test_crtc_enable_vblank_vupdate_busy()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1491 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1547 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1689 const struct resource_pool *pool = dc->res_pool; in dcn30_split_stream_for_mpc_or_odm()
1757 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1774 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1812 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn30_internal_validate_bw()
1813 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn30_internal_validate_bw()
1864 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
1885 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
1906 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn30_internal_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c976 params[i].sink->ctx->dc->res_pool->dscs[0], in set_dsc_configs_from_fairness_vars()
1029 param.sink->ctx->dc->res_pool->dscs[0], in bpp_x16_from_pbn()
1273 stream->sink->ctx->dc->res_pool->dscs[0], in build_frl_mst_dsc_params()
1378 stream->sink->ctx->dc->res_pool->dscs[0], in compute_mst_dsc_configs_for_link()
1621 struct resource_pool *res_pool; in compute_mst_dsc_configs_for_state() local
1630 res_pool = stream->ctx->dc->res_pool; in compute_mst_dsc_configs_for_state()
1649 if (res_pool->funcs->remove_stream_from_ctx && in compute_mst_dsc_configs_for_state()
1650 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) in compute_mst_dsc_configs_for_state()
1917 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], in is_dsc_common_config_possible()
2081 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0], in dm_dp_mst_is_port_support_mode()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_dc_resource_mgmt.c985 ctx->config.callbacks.dc->res_pool, in unmap_dc_pipes_for_stream()
992 ctx->config.callbacks.dc->res_pool, in unmap_dc_pipes_for_stream()
1014 ctx->config.callbacks.dc->res_pool, in map_dc_pipes_for_stream()
1021 ctx->config.callbacks.dc->res_pool, in map_dc_pipes_for_stream()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1194 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1815 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1929 dc->res_pool->pipe_count); in dcn31_validate_bandwidth()
1954 if (dc->res_pool->funcs->calculate_wm_and_dlg) in dcn31_validate_bandwidth()
1955 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
2439 if (link->dc->res_pool->funcs->build_pipe_pix_clk_params) in dcn31_update_dc_state_for_encoder_switch()
2440 link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); in dcn31_update_dc_state_for_encoder_switch()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_panel_cntl.c101 uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz; in dcn31_panel_cntl_hw_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c188 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn60_update_clocks_update_dpp_dto()
288 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn60_build_update_display_clocks_sequence()
703 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( in dcn60_init_clocks()
1439 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( in dcn60_get_memclk_states_from_smu()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c198 for (i = 0; i < dc->res_pool->pipe_count; ++i) { in dcn35_disable_otg_wa()
264 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dtb_dto()
302 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dpp_dto()
330 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn35_update_clocks_update_dpp_dto()

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