| /linux/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-allocator.c | 37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
190 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
231 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
234 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
235 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
243 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
246 if (res_pool->hubbub) { in dcn201_init_hw()
247 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
249 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
251 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 96 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
138 struct abm **abms = dc->res_pool->multiple_abms; in dcn401_init_hw()
141 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
158 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
159 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
178 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn401_init_hw()
181 if (res_pool->hubbub) { in dcn401_init_hw()
182 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
184 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn401_init_hw()
186 current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn401_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 84 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
91 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_i… in dcn21_s0i3_golden_init_wa()
92 return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); in dcn21_s0i3_golden_init_wa()
183 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
216 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
259 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
292 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 218 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1206 struct dccg *dccg = dc->res_pool->dccg; in dce110_disable_stream()
1814 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1815 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1816 dc->res_pool->timing_generators[i]); in power_down_controllers()
1824 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1825 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1828 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
1829 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( in power_down_clock_sources()
1830 dc->res_pool->clock_sources[i]) == false) in power_down_clock_sources()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 232 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
345 if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { in dc_stream_check_cursor_attributes()
346 max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream); in dc_stream_check_cursor_attributes()
513 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
532 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
578 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
599 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
611 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
629 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
709 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
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| H A D | dc_resource.c | 270 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
275 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
279 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
283 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
288 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
292 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
296 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
300 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
304 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
310 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_factory.c | 398 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
399 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
558 if (link->dc->res_pool->funcs->link_init) in construct_phy()
559 link->dc->res_pool->funcs->link_init(link); in construct_phy()
616 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
730 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
731 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
735 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
742 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
903 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
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| H A D | link_detection.c | 202 aud_support = &link->dc->res_pool->audio_support; in link_detect_sink_signal_type()
589 struct audio_support *audio_support = &link->dc->res_pool->audio_support; in detect_dp()
831 link->dc->res_pool->funcs->link_encs_assign && in should_verify_link_capability_destructively()
963 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in detect_link_and_local_sink()
1333 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) in detect_link_and_local_sink()
1334 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); in detect_link_and_local_sink()
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| H A D | link_resource.c | 84 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count; in link_restore_res_map()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1329 struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool; in build_pipe_hw_param()
1368 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1421 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1459 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1522 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
1643 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1686 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1758 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1781 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1803 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 522 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box_fpu()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box_fpu()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box_fpu()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box_fpu()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box_fpu()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 342 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
487 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
564 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
575 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
609 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
683 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
686 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
707 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
736 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
818 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 997 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1048 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
1063 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
1151 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); in dcn20_calculate_dlg_params()
1179 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1224 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1326 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1350 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1368 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
1726 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1365 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1420 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1562 const struct resource_pool *pool = dc->res_pool; in dcn30_split_stream_for_mpc_or_odm()
1630 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1647 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1684 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn30_internal_validate_bw()
1685 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn30_internal_validate_bw()
1736 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
1757 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
1778 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn30_internal_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/modules/power/ |
| H A D | power_helpers.c | 705 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
715 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
772 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
773 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
774 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
776 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
777 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); in dmub_init_abm_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_wrapper_fpu.c | 134 if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dml21_calculate_rq_and_dlg_params()
135 …context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, cont… in dml21_calculate_rq_and_dlg_params()
239 if (in_dc->res_pool->funcs->program_mcache_pipe_config) { in dml21_mode_check_and_programming()
250 …dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pip… in dml21_mode_check_and_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 76 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
129 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 926 params[i].sink->ctx->dc->res_pool->dscs[0], in set_dsc_configs_from_fairness_vars()
979 param.sink->ctx->dc->res_pool->dscs[0], in bpp_x16_from_pbn()
1248 stream->sink->ctx->dc->res_pool->dscs[0], in compute_mst_dsc_configs_for_link()
1491 struct resource_pool *res_pool; in compute_mst_dsc_configs_for_state() local
1500 res_pool = stream->ctx->dc->res_pool; in compute_mst_dsc_configs_for_state()
1519 if (res_pool->funcs->remove_stream_from_ctx && in compute_mst_dsc_configs_for_state()
1520 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) in compute_mst_dsc_configs_for_state()
1787 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], in is_dsc_common_config_possible()
1948 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0], in dm_dp_mst_is_port_support_mode()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 815 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); in dcn21_fast_validate_bw()
854 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
878 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
888 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
907 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
923 &context->res_ctx, dc->res_pool, in dcn21_fast_validate_bw()
966 dc->res_pool->pipe_count); in dcn21_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_capability.c | 285 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; in get_clock_source_id()
344 struct resource_pool *res_pool = link->dc->res_pool; in dp_is_fec_supported() local
345 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_is_fec_supported()
2296 struct resource_pool *res_pool = link->dc->res_pool; in dp_get_max_link_enc_cap() local
2297 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_get_max_link_enc_cap()
2335 struct resource_pool *res_pool = link->dc->res_pool; in dp_get_max_link_cap() local
2336 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); in dp_get_max_link_cap()
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