| /linux/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-allocator.c | 37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
190 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
231 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
234 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
235 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
243 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
246 if (res_pool->hubbub) { in dcn201_init_hw()
247 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
249 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
251 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 96 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
97 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
100 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd… in enable_memory_low_power()
102 for (i = 0; i < dc->res_pool->stream_enc_count; i++) in enable_memory_low_power()
103 if (dc->res_pool->stream_enc[i]->vpg) in enable_memory_low_power()
104 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
105 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) in enable_memory_low_power()
106 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->… in enable_memory_low_power()
113 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
116 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 102 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
103 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
105 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
107 for (i = 0; i < dc->res_pool->stream_enc_count; i++)
108 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
110 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
111 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->…
120 if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { in print_pg_status()
121 if (dc->res_pool->pg_cntl->funcs->print_pg_status) in print_pg_status()
122 dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); in print_pg_status()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 79 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
262 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
363 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_program_gamut_remap()
399 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
441 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
442 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
446 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
459 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
481 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
495 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 238 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
250 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_calculate_cab_allocation()
251 num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes); in dcn32_calculate_cab_allocation()
360 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
391 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
412 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
452 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
488 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
534 struct mpc *mpc = dc->res_pool->mpc; in dcn32_set_input_transfer_func()
574 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 92 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
138 struct abm **abms = dc->res_pool->multiple_abms; in dcn401_init_hw()
141 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
157 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
158 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
177 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn401_init_hw()
180 if (res_pool->hubbub) { in dcn401_init_hw()
181 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
183 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn401_init_hw()
185 current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn401_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 79 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
193 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
195 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
197 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
243 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
247 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
251 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
269 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
273 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
277 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 89 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
229 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
274 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
298 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
454 struct resource_pool *pool = dc->res_pool; in dcn10_log_color_state()
615 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
1037 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
1057 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
1066 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
1067 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 84 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
91 …if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_i… in dcn21_s0i3_golden_init_wa()
92 return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); in dcn21_s0i3_golden_init_wa()
183 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
216 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
259 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
292 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 221 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
335 if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { in dc_stream_check_cursor_attributes()
336 max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream); in dc_stream_check_cursor_attributes()
503 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
522 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
566 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
587 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
599 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
617 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
697 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
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| H A D | dc.c | 265 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
342 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
343 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
356 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
358 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
360 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
361 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
364 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
365 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
386 if (!dc->res_pool) in destroy_link_encoders()
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| H A D | dc_resource.c | 266 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
271 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
275 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
279 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
284 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
288 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
292 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
296 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
300 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
306 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| H A D | dc_state.c | 297 if (dc->res_pool) in dc_state_construct()
381 if (state->stream_count >= dc->res_pool->timing_generator_count) { in dc_state_add_stream()
391 state, dc->res_pool, stream); in dc_state_add_stream()
416 dc->current_state, dc->res_pool, stream, 1); in dc_state_remove_stream()
418 state, dc->res_pool, stream); in dc_state_remove_stream()
458 new_ctx, cur_ctx, dc->res_pool, in remove_mpc_combine_for_stream()
468 struct resource_pool *pool = dc->res_pool; in dc_state_add_plane()
508 dc->current_state, dc->res_pool, stream, in dc_state_add_plane()
538 struct resource_pool *pool = dc->res_pool; in dc_state_remove_plane()
923 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_state_remove_phantom_streams_and_planes()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 216 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1142 struct dccg *dccg = dc->res_pool->dccg; in dce110_disable_stream()
1746 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1747 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1748 dc->res_pool->timing_generators[i]); in power_down_controllers()
1756 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1757 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1760 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
1761 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( in power_down_clock_sources()
1762 dc->res_pool->clock_sources[i]) == false) in power_down_clock_sources()
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_factory.c | 386 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
387 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
539 if (link->dc->res_pool->funcs->link_init) in construct_phy()
540 link->dc->res_pool->funcs->link_init(link); in construct_phy()
595 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
702 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
703 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
707 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
714 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
874 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1294 struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool; in build_pipe_hw_param()
1332 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1385 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1423 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1486 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
1606 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1649 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1720 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1743 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1765 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 522 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 402 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
434 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
477 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
487 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
516 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_print_pg_status()
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