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Searched refs:regval (Results 1 – 25 of 196) sorted by relevance

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/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-hw.c38 u32 regval; in xlgmac_disable_rx_csum() local
40 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
41 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_disable_rx_csum()
43 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
50 u32 regval; in xlgmac_enable_rx_csum() local
52 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
53 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_enable_rx_csum()
55 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
112 u32 regval; in xlgmac_enable_rx_vlan_stripping() local
114 regval = readl(pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_stripping()
[all …]
/linux/drivers/bus/mhi/ep/
H A Dmmio.c25 u32 regval; in mhi_ep_mmio_masked_write() local
27 regval = mhi_ep_mmio_read(mhi_cntrl, offset); in mhi_ep_mmio_masked_write()
28 regval &= ~mask; in mhi_ep_mmio_masked_write()
29 regval |= (val << __ffs(mask)) & mask; in mhi_ep_mmio_masked_write()
30 mhi_ep_mmio_write(mhi_cntrl, offset, regval); in mhi_ep_mmio_masked_write()
35 u32 regval; in mhi_ep_mmio_masked_read() local
37 regval = mhi_ep_mmio_read(dev, offset); in mhi_ep_mmio_masked_read()
38 regval &= mask; in mhi_ep_mmio_masked_read()
39 regval >>= __ffs(mask); in mhi_ep_mmio_masked_read()
41 return regval; in mhi_ep_mmio_masked_read()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-mchp-pci1xxxx.c373 u8 regval; in pci1xxxx_i2c_configure_smbalert_pin() local
375 regval = readb(p); in pci1xxxx_i2c_configure_smbalert_pin()
378 regval |= SMBALERT_MST_PU; in pci1xxxx_i2c_configure_smbalert_pin()
380 regval &= ~SMBALERT_MST_PU; in pci1xxxx_i2c_configure_smbalert_pin()
382 writeb(regval, p); in pci1xxxx_i2c_configure_smbalert_pin()
388 u8 regval; in pci1xxxx_i2c_send_start_stop() local
390 regval = readb(p); in pci1xxxx_i2c_send_start_stop()
393 regval |= SMB_CORE_CMD_START; in pci1xxxx_i2c_send_start_stop()
395 regval |= SMB_CORE_CMD_STOP; in pci1xxxx_i2c_send_start_stop()
397 writeb(regval, p); in pci1xxxx_i2c_send_start_stop()
[all …]
/linux/drivers/edac/
H A Dversal_edac.c252 u32 regval; in get_ce_error_info() local
259 regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET); in get_ce_error_info()
260 reghi = regval & ECCR_UE_CE_ADDR_HI_ROW_MASK; in get_ce_error_info()
261 p->ceinfo[0].i = regval | reghi << 32; in get_ce_error_info()
262 regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET); in get_ce_error_info()
269 regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET); in get_ce_error_info()
271 p->ceinfo[1].i = regval | reghi << 32; in get_ce_error_info()
272 regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET); in get_ce_error_info()
284 u32 regval; in get_ue_error_info() local
291 regval = readl(ddrmc_base + ECCR0_UE_ADDR_LO_OFFSET); in get_ue_error_info()
[all …]
H A Dsynopsys_edac.c370 u32 regval, clearval = 0; in zynq_get_error_info() local
376 regval = readl(base + STAT_OFST); in zynq_get_error_info()
377 if (!regval) in zynq_get_error_info()
380 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
381 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
383 regval = readl(base + CE_LOG_OFST); in zynq_get_error_info()
384 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
387 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
388 regval = readl(base + CE_ADDR_OFST); in zynq_get_error_info()
389 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
[all …]
/linux/drivers/power/supply/
H A Dadp5061.c177 unsigned int regval; in adp5061_get_input_current_limit() local
180 ret = regmap_read(st->regmap, ADP5061_VINX_SET, &regval); in adp5061_get_input_current_limit()
184 mode = ADP5061_VINX_SET_ILIM_MODE(regval); in adp5061_get_input_current_limit()
227 unsigned int regval; in adp5061_get_min_voltage() local
230 ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, &regval); in adp5061_get_min_voltage()
234 regval = ((regval & ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK) >> 3); in adp5061_get_min_voltage()
235 val->intval = adp5061_vmin[regval] * 1000; in adp5061_get_min_voltage()
243 unsigned int regval; in adp5061_get_chg_volt_lim() local
246 ret = regmap_read(st->regmap, ADP5061_TERM_SET, &regval); in adp5061_get_chg_volt_lim()
250 mode = ADP5061_TERM_SET_CHG_VLIM_MODE(regval); in adp5061_get_chg_volt_lim()
[all …]
/linux/drivers/net/ethernet/microchip/lan865x/
H A Dlan865x.c48 u32 regval; in lan865x_set_hw_macaddr_low_bytes() local
50 regval = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0]; in lan865x_set_hw_macaddr_low_bytes()
52 return oa_tc6_write_register(tc6, LAN865X_REG_MAC_L_SADDR1, regval); in lan865x_set_hw_macaddr_low_bytes()
58 u32 regval; in lan865x_set_hw_macaddr() local
67 regval = (mac[5] << 8) | mac[4]; in lan865x_set_hw_macaddr()
69 regval); in lan865x_set_hw_macaddr()
209 u32 regval = 0; in lan865x_multicast_work_handler() local
214 regval |= MAC_NET_CFG_PROMISCUOUS_MODE; in lan865x_multicast_work_handler()
215 regval &= (~MAC_NET_CFG_MULTICAST_MODE); in lan865x_multicast_work_handler()
216 regval &= (~MAC_NET_CFG_UNICAST_MODE); in lan865x_multicast_work_handler()
[all …]
/linux/drivers/rapidio/switches/
H A Didt_gen2.c199 u32 regval; in idtg2_get_domain() local
205 IDT_RIO_DOMAIN, &regval); in idtg2_get_domain()
207 *sw_domain = (u8)(regval & 0xff); in idtg2_get_domain()
215 u32 regval; in idtg2_em_init() local
240 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval); in idtg2_em_init()
242 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); in idtg2_em_init()
258 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval); in idtg2_em_init()
260 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | in idtg2_em_init()
280 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval); in idtg2_em_init()
282 regval | IDT_LANE_CTRL_GENPW); in idtg2_em_init()
[all …]
/linux/drivers/iio/proximity/
H A Dsx9310.c293 unsigned int regval, gain; in sx9310_read_gain() local
296 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL3, &regval); in sx9310_read_gain()
303 gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN0_MASK, regval); in sx9310_read_gain()
307 gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN12_MASK, regval); in sx9310_read_gain()
320 unsigned int regval; in sx9310_read_samp_freq() local
323 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &regval); in sx9310_read_samp_freq()
327 regval = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, regval); in sx9310_read_samp_freq()
328 *val = sx9310_samp_freq_table[regval].val; in sx9310_read_samp_freq()
329 *val2 = sx9310_samp_freq_table[regval].val2; in sx9310_read_samp_freq()
415 unsigned int regval; in sx9310_read_thresh() local
[all …]
H A Dsx9324.c389 unsigned int reg, regval; in sx9324_read_gain() local
393 ret = regmap_read(data->regmap, reg, &regval); in sx9324_read_gain()
397 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval); in sx9324_read_gain()
398 if (regval) in sx9324_read_gain()
399 regval--; in sx9324_read_gain()
400 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD || in sx9324_read_gain()
401 regval > SX9324_REG_PROX_CTRL0_GAIN_8) in sx9324_read_gain()
404 *val = 1 << regval; in sx9324_read_gain()
413 unsigned int regval; in sx9324_read_samp_freq() local
415 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &regval); in sx9324_read_samp_freq()
[all …]
H A Dsx9360.c283 unsigned int reg, regval; in sx9360_read_gain() local
287 ret = regmap_read(data->regmap, reg, &regval); in sx9360_read_gain()
291 *val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval); in sx9360_read_gain()
399 unsigned int regval; in sx9360_read_thresh() local
402 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, &regval); in sx9360_read_thresh()
406 if (regval <= 1) in sx9360_read_thresh()
407 *val = regval; in sx9360_read_thresh()
409 *val = (regval * regval) / 2; in sx9360_read_thresh()
416 unsigned int regval, pthresh; in sx9360_read_hysteresis() local
423 ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, &regval); in sx9360_read_hysteresis()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c69 u32 regval; in phy_berlin_sata_reg_setbits() local
75 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
76 regval &= ~mask; in phy_berlin_sata_reg_setbits()
77 regval |= val; in phy_berlin_sata_reg_setbits()
78 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
86 u32 regval; in phy_berlin_sata_power_on() local
94 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
95 regval &= ~desc->power_bit; in phy_berlin_sata_power_on()
96 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
100 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
[all …]
/linux/drivers/regulator/
H A Dab8500-ext.c115 u8 regval; in ab8500_ext_regulator_enable() local
127 regval = info->update_val_hp; in ab8500_ext_regulator_enable()
129 regval = info->update_val; in ab8500_ext_regulator_enable()
133 info->update_mask, regval); in ab8500_ext_regulator_enable()
143 info->update_mask, regval); in ab8500_ext_regulator_enable()
152 u8 regval; in ab8500_ext_regulator_disable() local
163 regval = info->update_val_hw; in ab8500_ext_regulator_disable()
165 regval = 0; in ab8500_ext_regulator_disable()
169 info->update_mask, regval); in ab8500_ext_regulator_disable()
179 info->update_mask, regval); in ab8500_ext_regulator_disable()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c31 u32 regval) in hisi_phase_regval_to_degrees() argument
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
45 u32 regval; in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
69 int regval; in hisi_clk_set_phase() local
72 regval = hisi_phase_degrees_to_regval(phase, degrees); in hisi_clk_set_phase()
73 if (regval < 0) in hisi_clk_set_phase()
74 return regval; in hisi_clk_set_phase()
[all …]
/linux/drivers/platform/mellanox/
H A Dmlxreg-io.c49 bool rw_flag, int regsize, u32 *regval) in mlxreg_io_get_reg() argument
53 ret = regmap_read(regmap, data->reg, regval); in mlxreg_io_get_reg()
73 *regval = !!(*regval & ~data->mask); in mlxreg_io_get_reg()
76 *regval &= data->mask; in mlxreg_io_get_reg()
78 *regval |= ~data->mask; in mlxreg_io_get_reg()
84 *regval = ror32(*regval & data->mask, (data->bit - 1)); in mlxreg_io_get_reg()
89 *regval = (*regval & ~data->mask) | in_val; in mlxreg_io_get_reg()
102 *regval |= rol32(val, regsize * i * 8); in mlxreg_io_get_reg()
117 u32 regval = 0; in mlxreg_io_attr_show() local
123 priv->regsize, &regval); in mlxreg_io_attr_show()
[all …]
H A Dmlxreg-hotplug.c214 u32 regval; in mlxreg_hotplug_attr_show() local
221 ret = regmap_read(priv->regmap, data->reg, &regval); in mlxreg_hotplug_attr_show()
226 regval &= data->mask; in mlxreg_hotplug_attr_show()
230 regval = !(regval & data->mask); in mlxreg_hotplug_attr_show()
232 regval = !!(regval & data->mask); in mlxreg_hotplug_attr_show()
235 return sysfs_emit(buf, "%u\n", regval); in mlxreg_hotplug_attr_show()
258 u32 regval; in mlxreg_hotplug_attr_init() local
273 &regval); in mlxreg_hotplug_attr_init()
277 item->mask = GENMASK((regval & item->mask) - 1, 0); in mlxreg_hotplug_attr_init()
293 data->capability, &regval); in mlxreg_hotplug_attr_init()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c381 u32 regval; in ar9002_hw_antdiv_comb_conf_get() local
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
384 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
386 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
388 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> in ar9002_hw_antdiv_comb_conf_get()
398 u32 regval; in ar9002_hw_antdiv_comb_conf_set() local
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
401 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | in ar9002_hw_antdiv_comb_conf_set()
404 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
406 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
[all …]
/linux/drivers/firmware/xilinx/
H A Dzynqmp-ufs.c38 u32 regval; in zynqmp_pm_is_mphy_tx_rx_config_ready() local
44 ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, &regval); in zynqmp_pm_is_mphy_tx_rx_config_ready()
48 regval &= TX_RX_CFG_RDY_MASK; in zynqmp_pm_is_mphy_tx_rx_config_ready()
49 if (regval) in zynqmp_pm_is_mphy_tx_rx_config_ready()
66 u32 regval; in zynqmp_pm_is_sram_init_done() local
72 ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &regval); in zynqmp_pm_is_sram_init_done()
76 regval &= SRAM_CSR_INIT_DONE_MASK; in zynqmp_pm_is_sram_init_done()
77 if (regval) in zynqmp_pm_is_sram_init_done()
/linux/drivers/pinctrl/
H A Dpinctrl-artpec6.c657 unsigned int regval, val; in artpec6_pmx_select_func() local
684 regval = readl(pmx->base + reg); in artpec6_pmx_select_func()
685 regval &= ~ARTPEC6_PINMUX_SEL_MASK; in artpec6_pmx_select_func()
686 regval |= val; in artpec6_pmx_select_func()
687 writel(regval, pmx->base + reg); in artpec6_pmx_select_func()
738 unsigned int regval; in artpec6_pconf_get() local
751 regval = readl(pmx->base + artpec6_pmx_reg_offset(pin)); in artpec6_pconf_get()
756 if (!(regval & ARTPEC6_PINMUX_UDC1_MASK)) in artpec6_pconf_get()
762 if (regval & ARTPEC6_PINMUX_UDC1_MASK) in artpec6_pconf_get()
765 regval = regval & ARTPEC6_PINMUX_UDC0_MASK; in artpec6_pconf_get()
[all …]
/linux/sound/x86/
H A Dintel_hdmi_lpe_audio.h124 u32 regval; member
148 u32 regval; member
167 u32 regval; member
182 u32 regval; member
192 u32 regval; member
204 u32 regval; member
223 u32 regval; member
236 u32 regval; member
248 u32 regval; member
265 u32 regval; member
[all …]
/linux/drivers/clk/qcom/
H A Dclk-krait.c26 u32 regval; in __krait_mux_set_sel() local
30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel()
34 regval |= SECCLKAGD; in __krait_mux_set_sel()
35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel()
39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
41 regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); in __krait_mux_set_sel()
42 regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); in __krait_mux_set_sel()
44 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
48 regval &= ~SECCLKAGD; in __krait_mux_set_sel()
[all …]
/linux/drivers/watchdog/
H A Dmlx_wdt.c59 u32 regval; in mlxreg_wdt_check_card_reset() local
69 rc = regmap_read(wdt->regmap, reg_data->reg, &regval); in mlxreg_wdt_check_card_reset()
71 if (regval & ~reg_data->mask) { in mlxreg_wdt_check_card_reset()
111 u32 regval, set_time, hw_timeout; in mlxreg_wdt_set_timeout() local
116 rc = regmap_read(wdt->regmap, reg_data->reg, &regval); in mlxreg_wdt_set_timeout()
121 regval = (regval & reg_data->mask) | hw_timeout; in mlxreg_wdt_set_timeout()
124 rc = regmap_write(wdt->regmap, reg_data->reg, regval); in mlxreg_wdt_set_timeout()
134 regval = timeout & 0xff; in mlxreg_wdt_set_timeout()
135 rc = regmap_write(wdt->regmap, reg_data->reg, regval); in mlxreg_wdt_set_timeout()
137 regval = (timeout & 0xff00) >> 8; in mlxreg_wdt_set_timeout()
[all …]
/linux/sound/soc/codecs/
H A Dadau7118.c152 u32 regval; in adau7118_set_fmt() local
189 regval = ADAU7118_LRCLK_BCLK_POL(0); in adau7118_set_fmt()
192 regval = ADAU7118_LRCLK_BCLK_POL(2); in adau7118_set_fmt()
195 regval = ADAU7118_LRCLK_BCLK_POL(1); in adau7118_set_fmt()
198 regval = ADAU7118_LRCLK_BCLK_POL(3); in adau7118_set_fmt()
209 regval); in adau7118_set_fmt()
241 u32 regval; in adau7118_set_tdm_slot() local
247 regval = ADAU7118_SLOT_WIDTH(0); in adau7118_set_tdm_slot()
250 regval = ADAU7118_SLOT_WIDTH(2); in adau7118_set_tdm_slot()
253 regval in adau7118_set_tdm_slot()
280 u32 regval; adau7118_hw_params() local
484 u32 clk_map[4], regval; adau7118_parset_dt() local
[all...]
/linux/drivers/iio/adc/
H A Dmeson_saradc.c393 u32 regval; in meson_sar_adc_get_fifo_count() local
395 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_get_fifo_count()
397 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); in meson_sar_adc_get_fifo_count()
431 u32 regval; in meson_sar_adc_set_chan7_mux() local
433 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); in meson_sar_adc_set_chan7_mux()
435 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); in meson_sar_adc_set_chan7_mux()
448 int regval, fifo_chan, fifo_val, count; in meson_sar_adc_read_raw_sample() local
460 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval); in meson_sar_adc_read_raw_sample()
461 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); in meson_sar_adc_read_raw_sample()
468 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); in meson_sar_adc_read_raw_sample()
[all …]
H A Dmcp3911.c560 u32 regval; in mcp3911_config() local
563 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &regval, 2); in mcp3911_config()
567 regval &= ~MCP3911_CONFIG_VREFEXT; in mcp3911_config()
570 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); in mcp3911_config()
573 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); in mcp3911_config()
576 regval &= ~MCP3911_CONFIG_CLKEXT; in mcp3911_config()
579 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); in mcp3911_config()
582 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); in mcp3911_config()
585 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); in mcp3911_config()
589 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, &regval, 2); in mcp3911_config()
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