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Searched refs:regval (Results 1 – 25 of 247) sorted by relevance

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/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-hw.c38 u32 regval; in xlgmac_disable_rx_csum() local
40 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
41 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_disable_rx_csum()
43 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
50 u32 regval; in xlgmac_enable_rx_csum() local
52 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
53 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_enable_rx_csum()
55 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
112 u32 regval; in xlgmac_enable_rx_vlan_stripping() local
114 regval = readl(pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_stripping()
[all …]
/linux/drivers/bus/mhi/ep/
H A Dmmio.c25 u32 regval; in mhi_ep_mmio_masked_write() local
27 regval = mhi_ep_mmio_read(mhi_cntrl, offset); in mhi_ep_mmio_masked_write()
28 regval &= ~mask; in mhi_ep_mmio_masked_write()
29 regval |= (val << __ffs(mask)) & mask; in mhi_ep_mmio_masked_write()
30 mhi_ep_mmio_write(mhi_cntrl, offset, regval); in mhi_ep_mmio_masked_write()
35 u32 regval; in mhi_ep_mmio_masked_read() local
37 regval = mhi_ep_mmio_read(dev, offset); in mhi_ep_mmio_masked_read()
38 regval &= mask; in mhi_ep_mmio_masked_read()
39 regval >>= __ffs(mask); in mhi_ep_mmio_masked_read()
41 return regval; in mhi_ep_mmio_masked_read()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_csc_v.c132 tbl_entry->regval[0], in program_color_matrix_v()
138 tbl_entry->regval[1], in program_color_matrix_v()
150 tbl_entry->regval[2], in program_color_matrix_v()
156 tbl_entry->regval[3], in program_color_matrix_v()
168 tbl_entry->regval[4], in program_color_matrix_v()
174 tbl_entry->regval[5], in program_color_matrix_v()
186 tbl_entry->regval[6], in program_color_matrix_v()
192 tbl_entry->regval[7], in program_color_matrix_v()
204 tbl_entry->regval[8], in program_color_matrix_v()
210 tbl_entry->regval[9], in program_color_matrix_v()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-mchp-pci1xxxx.c373 u8 regval; in pci1xxxx_i2c_configure_smbalert_pin() local
375 regval = readb(p); in pci1xxxx_i2c_configure_smbalert_pin()
378 regval |= SMBALERT_MST_PU; in pci1xxxx_i2c_configure_smbalert_pin()
380 regval &= ~SMBALERT_MST_PU; in pci1xxxx_i2c_configure_smbalert_pin()
382 writeb(regval, p); in pci1xxxx_i2c_configure_smbalert_pin()
388 u8 regval; in pci1xxxx_i2c_send_start_stop() local
390 regval = readb(p); in pci1xxxx_i2c_send_start_stop()
393 regval |= SMB_CORE_CMD_START; in pci1xxxx_i2c_send_start_stop()
395 regval |= SMB_CORE_CMD_STOP; in pci1xxxx_i2c_send_start_stop()
397 writeb(regval, p); in pci1xxxx_i2c_send_start_stop()
[all …]
/linux/drivers/spi/
H A Dspi-pci1xxxx.c212 u32 regval; in pci1xxxx_acquire_sys_lock() local
214 return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval, in pci1xxxx_acquire_sys_lock()
215 (regval & SPI_SYSLOCK), 100, in pci1xxxx_acquire_sys_lock()
228 u32 regval; in pci1xxxx_check_spi_can_dma() local
244 regval = readl(spi_bus->reg_base + DEV_REV_REG); in pci1xxxx_check_spi_can_dma()
245 spi_bus->dev_rev = regval & DEV_REV_MASK; in pci1xxxx_check_spi_can_dma()
247 regval = readl(spi_bus->reg_base + in pci1xxxx_check_spi_can_dma()
249 pf_num = regval & SPI_PERI_ENBLE_PF_MASK; in pci1xxxx_check_spi_can_dma()
282 u32 regval; in pci1xxxx_spi_dma_config() local
309 regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA); in pci1xxxx_spi_dma_config()
[all …]
/linux/drivers/hwmon/
H A Dmax31730.c84 u8 regval = *confdata; in max31730_set_enable() local
88 regval |= BIT(channel); in max31730_set_enable()
90 regval &= ~BIT(channel); in max31730_set_enable()
92 if (regval != *confdata) { in max31730_set_enable()
93 err = i2c_smbus_write_byte_data(client, reg, regval); in max31730_set_enable()
96 *confdata = regval; in max31730_set_enable()
119 int regval, reg, offset; in max31730_read() local
153 regval = i2c_smbus_read_byte_data(data->client, in max31730_read()
155 if (regval < 0) in max31730_read()
156 return regval; in max31730_read()
[all …]
H A Dmax6621.c167 static int max6621_verify_reg_data(struct device *dev, int regval) in max6621_verify_reg_data() argument
169 if (regval >= MAX6621_PECI_ERR_MIN && in max6621_verify_reg_data()
170 regval <= MAX6621_PECI_ERR_MAX) { in max6621_verify_reg_data()
172 regval); in max6621_verify_reg_data()
177 switch (regval) { in max6621_verify_reg_data()
180 regval); in max6621_verify_reg_data()
183 dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval); in max6621_verify_reg_data()
187 regval); in max6621_verify_reg_data()
190 dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval); in max6621_verify_reg_data()
193 dev_dbg(dev, "No alert active - err 0x%04x.\n", regval); in max6621_verify_reg_data()
[all …]
H A Dmax31760.c81 unsigned int regval; in max31760_read() local
91 ret = regmap_read(state->regmap, REG_STATUS, &regval); in max31760_read()
95 *val = FIELD_GET(STATUS_RDFA, regval); in max31760_read()
99 ret = regmap_read(state->regmap, REG_STATUS, &regval); in max31760_read()
104 *val = FIELD_GET(STATUS_ALARM_MAX(1), regval); in max31760_read()
106 *val = FIELD_GET(STATUS_ALARM_MAX(0), regval); in max31760_read()
110 ret = regmap_read(state->regmap, REG_STATUS, &regval); in max31760_read()
115 *val = FIELD_GET(STATUS_ALARM_CRIT(1), regval); in max31760_read()
117 *val = FIELD_GET(STATUS_ALARM_CRIT(0), regval); in max31760_read()
153 ret = regmap_read(state->regmap, REG_STATUS, &regval); in max31760_read()
[all …]
H A Dlm83.c179 unsigned int regval; in lm83_temp_read() local
184 err = regmap_read(data->regmap, LM83_REG_TEMP[channel], &regval); in lm83_temp_read()
187 *val = (s8)regval * 1000; in lm83_temp_read()
190 err = regmap_read(data->regmap, LM83_REG_MAX[channel], &regval); in lm83_temp_read()
193 *val = (s8)regval * 1000; in lm83_temp_read()
196 err = regmap_read(data->regmap, LM83_REG_R_TCRIT, &regval); in lm83_temp_read()
199 *val = (s8)regval * 1000; in lm83_temp_read()
202 err = regmap_read(data->regmap, LM83_ALARM_REG[channel], &regval); in lm83_temp_read()
205 *val = !!(regval & LM83_MAX_ALARM_BIT[channel]); in lm83_temp_read()
208 err = regmap_read(data->regmap, LM83_ALARM_REG[channel], &regval); in lm83_temp_read()
[all …]
H A Dmlxreg-fan.c128 u32 regval; in mlxreg_fan_read() local
141 err = regmap_read(fan->regmap, tacho->prsnt, &regval); in mlxreg_fan_read()
151 regval) { in mlxreg_fan_read()
158 err = regmap_read(fan->regmap, tacho->reg, &regval); in mlxreg_fan_read()
162 if (MLXREG_FAN_GET_FAULT(regval, tacho->mask)) { in mlxreg_fan_read()
168 *val = MLXREG_FAN_GET_RPM(regval, fan->divider, in mlxreg_fan_read()
173 err = regmap_read(fan->regmap, tacho->reg, &regval); in mlxreg_fan_read()
177 *val = MLXREG_FAN_GET_FAULT(regval, tacho->mask); in mlxreg_fan_read()
189 err = regmap_read(fan->regmap, pwm->reg, &regval); in mlxreg_fan_read()
193 *val = regval; in mlxreg_fan_read()
[all …]
/linux/drivers/edac/
H A Dversal_edac.c252 u32 regval; in get_ce_error_info() local
259 regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET); in get_ce_error_info()
260 reghi = regval & ECCR_UE_CE_ADDR_HI_ROW_MASK; in get_ce_error_info()
261 p->ceinfo[0].i = regval | reghi << 32; in get_ce_error_info()
262 regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET); in get_ce_error_info()
269 regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET); in get_ce_error_info()
271 p->ceinfo[1].i = regval | reghi << 32; in get_ce_error_info()
272 regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET); in get_ce_error_info()
284 u32 regval; in get_ue_error_info() local
291 regval = readl(ddrmc_base + ECCR0_UE_ADDR_LO_OFFSET); in get_ue_error_info()
[all …]
/linux/drivers/power/supply/
H A Dadp5061.c178 unsigned int regval; in adp5061_get_input_current_limit() local
181 ret = regmap_read(st->regmap, ADP5061_VINX_SET, &regval); in adp5061_get_input_current_limit()
185 mode = ADP5061_VINX_SET_ILIM_MODE(regval); in adp5061_get_input_current_limit()
228 unsigned int regval; in adp5061_get_min_voltage() local
231 ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, &regval); in adp5061_get_min_voltage()
235 regval = ((regval & ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK) >> 3); in adp5061_get_min_voltage()
236 val->intval = adp5061_vmin[regval] * 1000; in adp5061_get_min_voltage()
244 unsigned int regval; in adp5061_get_chg_volt_lim() local
247 ret = regmap_read(st->regmap, ADP5061_TERM_SET, &regval); in adp5061_get_chg_volt_lim()
251 mode = ADP5061_TERM_SET_CHG_VLIM_MODE(regval); in adp5061_get_chg_volt_lim()
[all …]
H A Dmax8971_charger.c126 u32 regval; in max8971_get_status() local
129 err = regmap_field_read(priv->rfield[CHG_DTLS], &regval); in max8971_get_status()
133 switch (regval) { in max8971_get_status()
161 u32 regval; in max8971_get_charge_type() local
164 err = regmap_field_read(priv->rfield[CHG_DTLS], &regval); in max8971_get_charge_type()
168 switch (regval) { in max8971_get_charge_type()
196 u32 regval; in max8971_get_health() local
199 err = regmap_field_read(priv->rfield[THM_DTLS], &regval); in max8971_get_health()
203 switch (regval) { in max8971_get_health()
229 u32 regval; in max8971_get_online() local
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c278 u32 i, regval; in ma35_pinmux_set_mux() local
284 regmap_read(npctl->regmap, setting->offset, &regval); in ma35_pinmux_set_mux()
285 regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1, in ma35_pinmux_set_mux()
287 regval |= setting->muxval << setting->shift; in ma35_pinmux_set_mux()
288 regmap_write(npctl->regmap, setting->offset, regval); in ma35_pinmux_set_mux()
304 u32 regval = readl(reg_mode); in ma35_gpio_set_mode() local
306 regval &= ~MA35_GP_MODE_MASK(gpio); in ma35_gpio_set_mode()
307 regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode); in ma35_gpio_set_mode()
309 writel(regval, reg_mode); in ma35_gpio_set_mode()
314 u32 regval = readl(reg_mode); in ma35_gpio_get_mode() local
[all …]
/linux/drivers/net/ethernet/microchip/lan865x/
H A Dlan865x.c48 u32 regval; in lan865x_set_hw_macaddr_low_bytes() local
50 regval = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0]; in lan865x_set_hw_macaddr_low_bytes()
52 return oa_tc6_write_register(tc6, LAN865X_REG_MAC_L_SADDR1, regval); in lan865x_set_hw_macaddr_low_bytes()
58 u32 regval; in lan865x_set_hw_macaddr() local
67 regval = (mac[5] << 8) | mac[4]; in lan865x_set_hw_macaddr()
69 regval); in lan865x_set_hw_macaddr()
209 u32 regval = 0; in lan865x_multicast_work_handler() local
214 regval |= MAC_NET_CFG_PROMISCUOUS_MODE; in lan865x_multicast_work_handler()
215 regval &= (~MAC_NET_CFG_MULTICAST_MODE); in lan865x_multicast_work_handler()
216 regval &= (~MAC_NET_CFG_UNICAST_MODE); in lan865x_multicast_work_handler()
[all …]
/linux/drivers/iio/proximity/
H A Dsx9310.c294 unsigned int regval, gain; in sx9310_read_gain() local
297 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL3, &regval); in sx9310_read_gain()
304 gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN0_MASK, regval); in sx9310_read_gain()
308 gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN12_MASK, regval); in sx9310_read_gain()
321 unsigned int regval; in sx9310_read_samp_freq() local
324 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &regval); in sx9310_read_samp_freq()
328 regval = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, regval); in sx9310_read_samp_freq()
329 *val = sx9310_samp_freq_table[regval].val; in sx9310_read_samp_freq()
330 *val2 = sx9310_samp_freq_table[regval].val2; in sx9310_read_samp_freq()
416 unsigned int regval; in sx9310_read_thresh() local
[all …]
H A Dsx9324.c390 unsigned int reg, regval; in sx9324_read_gain() local
394 ret = regmap_read(data->regmap, reg, &regval); in sx9324_read_gain()
398 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval); in sx9324_read_gain()
399 if (regval) in sx9324_read_gain()
400 regval--; in sx9324_read_gain()
401 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD || in sx9324_read_gain()
402 regval > SX9324_REG_PROX_CTRL0_GAIN_8) in sx9324_read_gain()
405 *val = 1 << regval; in sx9324_read_gain()
414 unsigned int regval; in sx9324_read_samp_freq() local
416 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &regval); in sx9324_read_samp_freq()
[all …]
/linux/drivers/rapidio/switches/
H A Didt_gen2.c199 u32 regval; in idtg2_get_domain() local
205 IDT_RIO_DOMAIN, &regval); in idtg2_get_domain()
207 *sw_domain = (u8)(regval & 0xff); in idtg2_get_domain()
215 u32 regval; in idtg2_em_init() local
240 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval); in idtg2_em_init()
242 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); in idtg2_em_init()
258 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval); in idtg2_em_init()
260 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | in idtg2_em_init()
280 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval); in idtg2_em_init()
282 regval | IDT_LANE_CTRL_GENPW); in idtg2_em_init()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c69 u32 regval; in phy_berlin_sata_reg_setbits() local
75 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
76 regval &= ~mask; in phy_berlin_sata_reg_setbits()
77 regval |= val; in phy_berlin_sata_reg_setbits()
78 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
86 u32 regval; in phy_berlin_sata_power_on() local
94 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
95 regval &= ~desc->power_bit; in phy_berlin_sata_power_on()
96 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
100 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
[all …]
/linux/drivers/regulator/
H A Dab8500-ext.c115 u8 regval; in ab8500_ext_regulator_enable() local
127 regval = info->update_val_hp; in ab8500_ext_regulator_enable()
129 regval = info->update_val; in ab8500_ext_regulator_enable()
133 info->update_mask, regval); in ab8500_ext_regulator_enable()
143 info->update_mask, regval); in ab8500_ext_regulator_enable()
152 u8 regval; in ab8500_ext_regulator_disable() local
163 regval = info->update_val_hw; in ab8500_ext_regulator_disable()
165 regval = 0; in ab8500_ext_regulator_disable()
169 info->update_mask, regval); in ab8500_ext_regulator_disable()
179 info->update_mask, regval); in ab8500_ext_regulator_disable()
[all …]
/linux/drivers/platform/mellanox/
H A Dmlxreg-io.c49 bool rw_flag, int regsize, u32 *regval) in mlxreg_io_get_reg() argument
53 ret = regmap_read(regmap, data->reg, regval); in mlxreg_io_get_reg()
73 *regval = !!(*regval & ~data->mask); in mlxreg_io_get_reg()
76 *regval &= data->mask; in mlxreg_io_get_reg()
78 *regval |= ~data->mask; in mlxreg_io_get_reg()
84 *regval = ror32(*regval & data->mask, (data->bit - 1)); in mlxreg_io_get_reg()
89 *regval = (*regval & ~data->mask) | in_val; in mlxreg_io_get_reg()
102 *regval |= rol32(val, regsize * i * 8); in mlxreg_io_get_reg()
117 u32 regval = 0; in mlxreg_io_attr_show() local
123 priv->regsize, &regval); in mlxreg_io_attr_show()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c31 u32 regval) in hisi_phase_regval_to_degrees() argument
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
45 u32 regval; in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
69 int regval; in hisi_clk_set_phase() local
72 regval = hisi_phase_degrees_to_regval(phase, degrees); in hisi_clk_set_phase()
73 if (regval < 0) in hisi_clk_set_phase()
74 return regval; in hisi_clk_set_phase()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c381 u32 regval; in ar9002_hw_antdiv_comb_conf_get() local
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
384 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
386 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
388 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> in ar9002_hw_antdiv_comb_conf_get()
398 u32 regval; in ar9002_hw_antdiv_comb_conf_set() local
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
401 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | in ar9002_hw_antdiv_comb_conf_set()
404 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
406 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
[all …]
/linux/drivers/iio/adc/
H A Dmeson_saradc.c393 u32 regval; in meson_sar_adc_get_fifo_count() local
395 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_sar_adc_get_fifo_count()
397 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); in meson_sar_adc_get_fifo_count()
431 u32 regval; in meson_sar_adc_set_chan7_mux() local
433 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); in meson_sar_adc_set_chan7_mux()
435 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); in meson_sar_adc_set_chan7_mux()
448 int regval, fifo_chan, fifo_val, count; in meson_sar_adc_read_raw_sample() local
460 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval); in meson_sar_adc_read_raw_sample()
461 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); in meson_sar_adc_read_raw_sample()
468 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); in meson_sar_adc_read_raw_sample()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-artpec6.c657 unsigned int regval, val; in artpec6_pmx_select_func() local
684 regval = readl(pmx->base + reg); in artpec6_pmx_select_func()
685 regval &= ~ARTPEC6_PINMUX_SEL_MASK; in artpec6_pmx_select_func()
686 regval |= val; in artpec6_pmx_select_func()
687 writel(regval, pmx->base + reg); in artpec6_pmx_select_func()
738 unsigned int regval; in artpec6_pconf_get() local
751 regval = readl(pmx->base + artpec6_pmx_reg_offset(pin)); in artpec6_pconf_get()
756 if (!(regval & ARTPEC6_PINMUX_UDC1_MASK)) in artpec6_pconf_get()
762 if (regval & ARTPEC6_PINMUX_UDC1_MASK) in artpec6_pconf_get()
765 regval = regval & ARTPEC6_PINMUX_UDC0_MASK; in artpec6_pconf_get()
[all …]

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