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Searched refs:regs_spill (Results 1 – 5 of 5) sorted by relevance

/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_save_crt0.S16 .globl regs_spill
17 regs_spill: label
24 stqa $0, regs_spill + 0
25 stqa $1, regs_spill + 16
26 stqa $2, regs_spill + 32
27 stqa $3, regs_spill + 48
28 stqa $4, regs_spill + 64
29 stqa $5, regs_spill + 80
30 stqa $6, regs_spill + 96
31 stqa $7, regs_spill + 112
[all …]
H A Dspu_restore_crt0.S17 .globl regs_spill
18 regs_spill: label
47 ila $3, regs_spill + 256
64 lqa $0, regs_spill + 0
65 lqa $1, regs_spill + 16
66 lqa $2, regs_spill + 32
67 lqa $3, regs_spill + 48
68 lqa $4, regs_spill + 64
69 lqa $5, regs_spill + 80
70 lqa $6, regs_spill + 96
[all …]
H A Dspu_restore.c34 unsigned int ls = (unsigned int)&regs_spill[0]; in fetch_regs_from_mem()
35 unsigned int size = sizeof(regs_spill); in fetch_regs_from_mem()
79 decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING; in restore_decr()
82 decr = regs_spill[offset].slot[0]; in restore_decr()
97 data = regs_spill[offset].slot[0]; in write_ppu_mb()
111 data = regs_spill[offset].slot[0]; in write_ppuint_mb()
125 fpcr = regs_spill[offset].v; in restore_fpcr()
138 srr0 = regs_spill[offset].slot[0]; in restore_srr0()
151 event_mask = regs_spill[offset].slot[0]; in restore_event_mask()
164 tag_mask = regs_spill[offset].slot[0]; in restore_tag_mask()
[all …]
H A Dspu_save.c33 regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask); in save_event_mask()
44 regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask); in save_tag_mask()
77 regs_spill[offset].v = spu_mffpscr(); in save_fpcr()
89 regs_spill[offset].slot[0] = spu_readch(SPU_RdDec); in save_decr()
101 regs_spill[offset].slot[0] = spu_readch(SPU_RdSRR0); in save_srr0()
106 unsigned int ls = (unsigned int)&regs_spill[0]; in spill_regs_to_mem()
107 unsigned int size = sizeof(regs_spill); in spill_regs_to_mem()
H A Dspu_utils.h44 extern spu_reg128v regs_spill[NR_SPU_SPILL_REGS];