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/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
88 * is added to the register which is referenced in the driver.
89 * Unreferenced register with no dont_generate_debug_code will result
96 * as the source and destination of any register accesses in our
97 * register window.
99 register MODE_PTR {
114 register INTSTAT {
131 register SEQINTCODE {
211 register CLRINT {
229 register ERROR {
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H A Daic7xxx.reg2 * Aic7xxx register and scratch ram definitions.
59 * is added to the register which is referenced in the driver.
60 * Unreferenced register with no dont_generate_debug_code will result
68 register SCSISEQ {
85 register SXFRCTL0 {
101 register SXFRCTL1 {
118 register SCSISIGI {
145 * Writing to this register modifies the control signals on the bus. Only
149 register SCSISIGO {
175 * Contents of this register determine the Synchronous SCSI data transfer
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/linux/Documentation/hwmon/
H A Ducd9200.rst62 in1_input Measured voltage. From READ_VIN register.
63 in1_min Minimum Voltage. From VIN_UV_WARN_LIMIT register.
64 in1_max Maximum voltage. From VIN_OV_WARN_LIMIT register.
65 in1_lcrit Critical minimum Voltage. VIN_UV_FAULT_LIMIT register.
67 register.
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
79 register.
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H A Dtps40422.rst48 in[1-2]_input Measured voltage. From READ_VOUT register.
51 curr[1-2]_input Measured current. From READ_IOUT register.
53 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
55 register.
60 temp1_input Measured temperature. From READ_TEMPERATURE_2 register
62 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
63 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
70 temp2_input Measured temperature. From READ_TEMPERATURE_2 register
H A Ducd9000.rst94 in[1-12]_input Measured voltage. From READ_VOUT register.
95 in[1-12]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
96 in[1-12]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
97 in[1-12]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
99 register.
108 curr[1-12]_input Measured current. From READ_IOUT register.
109 curr[1-12]_max Maximum current. From IOUT_OC_WARN_LIMIT register.
111 IOUT_UC_FAULT_LIMIT register.
113 register.
123 temp[1-2]_max Maximum temperature. From OT_WARN_LIMIT register.
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/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts114 compatible = "register-bit-led";
120 compatible = "register-bit-led";
126 compatible = "register-bit-led";
132 compatible = "register-bit-led";
138 compatible = "register-bit-led";
144 compatible = "register-bit-led";
150 compatible = "register-bit-led";
156 compatible = "register-bit-led";
163 compatible = "register-bit-led";
169 compatible = "register-bit-led";
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/linux/Documentation/devicetree/bindings/reset/
H A Dti-syscon-reset.txt7 sometimes a part of a larger register space region implementing various
8 functionalities. This register range is best represented as a syscon node to
10 register space.
30 - ti,reset-bits : Contains the reset control register information
34 register from the syscon register base
36 assert control register
38 register from the syscon register base
40 deassert control register
41 Cell #5 : offset of the reset status register
42 from the syscon register base
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/linux/Documentation/virt/kvm/arm/
H A Dvcpu-features.rst27 system. The ID register values may be VM-scoped in KVM, meaning that the
40 scheme for fields in ID register'. KVM does not allow ID register values that
44 It is **strongly recommended** that userspace modify the ID register values
45 before accessing the rest of the vCPU's CPU register state. KVM may use the
46 ID register values to control feature emulation. Interleaving ID register
47 modification with other system register accesses may lead to unpredictable
/linux/Documentation/PCI/endpoint/
H A Dpci-test-function.rst33 This register will be used to test BAR0. A known pattern will be written
34 and read back from MAGIC register to verify BAR0.
38 This register will be used by the host driver to indicate the function
54 This register reflects the status of the PCI endpoint device.
72 This register contains the source address (RC buffer address) for the
77 This register contains the destination address (RC buffer address) for
82 This register contains the interrupt type (Legacy/MSI) triggered
95 This register contains the triggered ID interrupt.
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic.rst28 register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
33 interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
58 GICv2 specs. Getting or setting such a register has the same effect as
59 reading or writing the register on the actual hardware from the cpu whose
62 vcpu_index used to access the register.
76 -ENXIO Getting or setting this register is not yet supported
92 defined in the GICv2 specs. Getting or setting such a register has the
93 same effect as reading or writing the register on the actual hardware.
98 guest. This interface always exposes four register APR[0-3] describing the
99 maximum possible 128 preemption levels. The semantics of the register
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/linux/Documentation/core-api/
H A Dprotection-keys.rst22 Protections for each key are defined with a per-CPU user-accessible register
23 (PKRU). Each of these is a 32-bit register storing two bits (Access Disable
26 Being a CPU register, PKRU is inherently thread-local, potentially giving each
30 register. The feature is only available in 64-bit mode, even though there is
41 register (POR_EL0). This is a 64-bit register encoding read, write and execute
44 Being a CPU register, POR_EL0 is inherently thread-local, potentially giving
61 application writes to the architecture specific CPU register directly in order
85 .. note:: pkey_set() is a wrapper around writing to the CPU register.
119 value for the protection key register and so will not be consistent with
120 userspace's value of the register or mprotect().
/linux/Documentation/devicetree/bindings/regulator/
H A Dlp872x.txt8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
19 bit[3]: BUCK2 output voltage register address. 1 = 0Ah, 0 = 0Bh
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
21 1 = register 08h, 0 = DVS
27 - ti,update-config: define it when LP872X_GENERAL_CFG register should be set
H A Dti-abb-regulator.txt9 - reg: Address and length of the register set for the device. It contains
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
15 - "int-address" - contains address of interrupt register for ABB module
25 - ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
48 - "ldo-address" - Contains address of ABB LDO override register.
51 register to provide override vset value.
53 override register to enable override vset value.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra30-ahub.txt8 - reg : Should contain the register physical address and length for each of
9 the AHUB's register blocks.
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
45 - ranges : The bus address mapping for the configlink register bus.
59 For RX CIFs, the numbers indicate the register number within AHUB routing
60 register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
37 - reg : offsets for the register set for controlling the DPLL.
39 "control" - contains the control register base address
40 "idlest" - contains the idle status register base address
41 "mult-div1" - contains the multiplier / divider register base address
42 "autoidle" - contains the autoidle register base address (optional)
44 the frequency spreading register base address (optional)
46 the modulation frequency register base address
48 ti,am3-* dpll types do not have autoidle register
H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt16 - reg : shall be the control register offset from PMC base for the pll clock.
36 - enable-reg : shall be the register offset from PMC base for the enable
37 register.
44 - divisor-reg : shall be the register offset from PMC base for the divisor
45 register.
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-dma.txt42 - reg: Should contain register location and length of the following dma
43 register regions. Register regions should be specified in the following
45 - Global control register region (global).
46 - Tx DMA channel configuration register region (txchan).
47 - Rx DMA channel configuration register region (rxchan).
48 - Tx DMA channel Scheduler configuration register region (txsched).
49 - Rx DMA flow configuration register region (rxflow).
52 - reg-names: Names for the register regions.
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic-msgr.txt4 representation of the message register blocks found in some FSL MPIC
9 - compatible: Specifies the compatibility list for the message register
15 message register block's addressable register space. The type shall be
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
34 An alias should be created for every message register block. They are not
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap2-dss.txt12 - reg: address and length of the register space
27 - reg: address and length of the register space
41 - reg: address and length of the register space
50 - reg: address and length of the register space
H A Dti,omap3-dss.txt12 - reg: address and length of the register space
34 - reg: address and length of the register space
50 - reg: address and length of the register space
61 - reg: address and length of the register space
77 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt14 The first region is external interface control register base and size(optional,
17 The second region is SerDes base register and size(optional, only used when
20 The third region is the PPE register base and size.
21 The fourth region is dsa fabric base register and size. It is not required for
29 - subctrl-syscon: is syscon handle for external interface control register.
40 - serdes-syscon: is syscon handle for SerDes register.
41 - cpld-syscon: is syscon handle + register offset pair for cpld register. It is
/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dguts.txt17 - reg : Offset and length of the register set for the device.
21 - fsl,has-rstcr : Indicates that the global utilities register set
22 contains a functioning "reset control register" (i.e. the board
23 is wired to reset upon setting the HRESET_REQ bit in this register).
/linux/Documentation/fb/
H A Dsa1100fb.rst32 lccr0:<value> Configure LCD control register 0 (11.7.3)
33 lccr1:<value> Configure LCD control register 1 (11.7.4)
34 lccr2:<value> Configure LCD control register 2 (11.7.5)
35 lccr3:<value> Configure LCD control register 3 (11.7.6)
/linux/tools/bpf/bpftool/Documentation/
H A Dbpftool-struct_ops.rst7 tool to register/unregister/introspect BPF struct_ops
22 { **show** | **list** | **dump** | **register** | **unregister** | **help** }
29 | **bpftool** **struct_ops register** *OBJ* [*LINK_DIR*]
54 bpftool struct_ops register *OBJ* [*LINK_DIR*]
87 **# bpftool struct_ops register bpf_cubic.o**

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