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Searched refs:regbase (Results 1 – 25 of 46) sorted by relevance

12

/linux/include/video/
H A Dvga.h200 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) in vga_mm_r() argument
202 return readb (regbase + port); in vga_mm_r()
205 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_mm_w() argument
207 writeb (val, regbase + port); in vga_mm_w()
210 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, in vga_mm_w_fast() argument
213 writew (VGA_OUT16VAL (val, reg), regbase + port); in vga_mm_w_fast()
237 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) in vga_r() argument
239 if (regbase) in vga_r()
240 return vga_mm_r (regbase, port); in vga_r()
245 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_w() argument
[all …]
/linux/drivers/video/fbdev/
H A Dcirrusfb.c356 u8 __iomem *regbase; member
396 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
397 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
402 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
411 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
413 caddr_t regbase,
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
639 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
645 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
649 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
[all …]
H A Dwm8505fb.c38 void __iomem *regbase; member
51 writel(0, fbi->regbase + i); in wm8505fb_init_hw()
54 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); in wm8505fb_init_hw()
55 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); in wm8505fb_init_hw()
62 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw()
63 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); in wm8505fb_init_hw()
66 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); in wm8505fb_init_hw()
67 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); in wm8505fb_init_hw()
70 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw()
71 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); in wm8505fb_init_hw()
[all …]
H A Dvt8500lcdfb.c112 control0 = readl(fbi->regbase) & ~0xf; in vt8500lcd_set_par()
113 writel(0, fbi->regbase); in vt8500lcd_set_par()
114 while (readl(fbi->regbase + 0x38) & 0x10) in vt8500lcd_set_par()
119 | (info->var.right_margin & 0xff), fbi->regbase + 0x4); in vt8500lcd_set_par()
123 | (info->var.lower_margin & 0xff), fbi->regbase + 0x8); in vt8500lcd_set_par()
125 | ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10); in vt8500lcd_set_par()
126 writel(0x80000000, fbi->regbase + 0x20); in vt8500lcd_set_par()
127 writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase); in vt8500lcd_set_par()
186 writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c); in vt8500lcd_ioctl()
188 readl(fbi->regbase + 0x38) & (1 << 3), HZ / 10); in vt8500lcd_ioctl()
[all …]
/linux/drivers/video/fbdev/core/
H A Dsvgalib.c24 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wcrt_multi() argument
29 regval = vga_rcrt(regbase, regset->regnum); in svga_wcrt_multi()
39 vga_wcrt(regbase, regset->regnum, regval); in svga_wcrt_multi()
45 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wseq_multi() argument
50 regval = vga_rseq(regbase, regset->regnum); in svga_wseq_multi()
60 vga_wseq(regbase, regset->regnum, regval); in svga_wseq_multi()
79 void svga_set_default_gfx_regs(void __iomem *regbase) in svga_set_default_gfx_regs() argument
82 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00); in svga_set_default_gfx_regs()
83 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00); in svga_set_default_gfx_regs()
84 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00); in svga_set_default_gfx_regs()
[all …]
/linux/drivers/rtc/
H A Drtc-sh.c89 void __iomem *regbase; member
104 tmp = readb(rtc->regbase + RCR1); in sh_rtc_alarm()
107 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_alarm()
124 tmp = readb(rtc->regbase + RCR1); in sh_rtc_alarm_irq_enable()
131 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_alarm_irq_enable()
143 if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN)) in sh_rtc_read_time()
151 tmp = readb(rtc->regbase + RCR1); in sh_rtc_read_time()
154 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_read_time()
156 sec128 = readb(rtc->regbase + R64CNT); in sh_rtc_read_time()
158 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); in sh_rtc_read_time()
[all …]
H A Drtc-vt8500.c73 void __iomem *regbase; member
88 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
89 writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
106 date = readl(vt8500_rtc->regbase + VT8500_RTC_DR); in vt8500_rtc_read_time()
107 time = readl(vt8500_rtc->regbase + VT8500_RTC_TR); in vt8500_rtc_read_time()
129 vt8500_rtc->regbase + VT8500_RTC_DS); in vt8500_rtc_set_time()
134 vt8500_rtc->regbase + VT8500_RTC_TS); in vt8500_rtc_set_time()
144 alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_read_alarm()
145 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_read_alarm()
167 vt8500_rtc->regbase + VT8500_RTC_AS); in vt8500_rtc_set_alarm()
[all …]
/linux/include/linux/
H A Dsvga.h71 static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data) in svga_wattr() argument
73 vga_r(regbase, VGA_IS1_RC); in svga_wattr()
74 vga_w(regbase, VGA_ATT_IW, index); in svga_wattr()
75 vga_w(regbase, VGA_ATT_W, data); in svga_wattr()
80 static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) in svga_wseq_mask() argument
82 vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & ~mask)); in svga_wseq_mask()
87 static inline void svga_wcrt_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) in svga_wcrt_mask() argument
89 vga_wcrt(regbase, index, (data & mask) | (vga_rcrt(regbase, index) & ~mask)); in svga_wcrt_mask()
100 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value);
101 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value);
[all …]
/linux/drivers/clocksource/
H A Dtimer-vt8500.c41 static void __iomem *regbase; variable
46 writel(3, regbase + TIMER_CTRL_VAL); in vt8500_timer_read()
47 while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) in vt8500_timer_read()
50 return readl(regbase + TIMER_COUNT_VAL); in vt8500_timer_read()
66 while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) in vt8500_timer_set_next_event()
69 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); in vt8500_timer_set_next_event()
74 writel(1, regbase + TIMER_IER_VAL); in vt8500_timer_set_next_event()
81 writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); in vt8500_shutdown()
82 writel(0, regbase + TIMER_IER_VAL); in vt8500_shutdown()
98 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_interrupt()
[all …]
/linux/arch/mips/rb532/
H A Dgpio.c52 void __iomem *regbase; member
102 return !!rb532_get_bit(offset, gpch->regbase + GPIOD); in rb532_gpio_get()
114 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_set()
129 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_input()
131 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); in rb532_gpio_direction_input()
146 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_output()
149 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_direction_output()
151 rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); in rb532_gpio_direction_output()
180 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); in rb532_gpio_set_ilevel()
189 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); in rb532_gpio_set_istat()
[all …]
/linux/drivers/spi/
H A Dspi-rockchip-sfc.c176 void __iomem *regbase; member
195 writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); in rockchip_sfc_reset()
197 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, in rockchip_sfc_reset()
204 writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_reset()
213 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); in rockchip_sfc_get_version()
242 reg = readl(sfc->regbase + SFC_IMR); in rockchip_sfc_irq_unmask()
244 writel(reg, sfc->regbase + SFC_IMR); in rockchip_sfc_irq_unmask()
252 reg = readl(sfc->regbase + SFC_IMR); in rockchip_sfc_irq_mask()
254 writel(reg, sfc->regbase + SFC_IMR); in rockchip_sfc_irq_mask()
259 writel(0, sfc->regbase + SFC_CTRL); in rockchip_sfc_init()
[all …]
/linux/drivers/gpio/
H A Dgpio-pxa.c65 void __iomem *regbase; member
164 return bank->regbase; in gpio_bank_base()
343 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase) in pxa_init_gpio_chip() argument
371 bank->regbase = regbase + BANK_OFF(i); in pxa_init_gpio_chip()
384 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
385 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
388 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
389 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
412 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
415 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
[all …]
H A Dgpio-f7188x.c88 unsigned int regbase; member
182 .regbase = _regbase, \
301 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
326 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_direction_in()
332 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in()
351 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get()
354 data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase)); in f7188x_gpio_get()
356 data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase)); in f7188x_gpio_get()
376 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase)); in f7188x_gpio_direction_out()
381 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out); in f7188x_gpio_direction_out()
[all …]
/linux/drivers/comedi/drivers/
H A Dcomedi_8255.c44 int dir, int port, int data, unsigned long regbase) in subdev_8255_io() argument
47 outb(data, dev->iobase + regbase + port); in subdev_8255_io()
50 return inb(dev->iobase + regbase + port); in subdev_8255_io()
56 int dir, int port, int data, unsigned long regbase) in subdev_8255_mmio() argument
59 writeb(data, dev->mmio + regbase + port); in subdev_8255_mmio()
62 return readb(dev->mmio + regbase + port); in subdev_8255_mmio()
190 unsigned long regbase) in subdev_8255_io_init() argument
192 return __subdev_8255_init(dev, s, subdev_8255_io, regbase); in subdev_8255_io_init()
209 unsigned long regbase) in subdev_8255_mm_init() argument
211 return __subdev_8255_init(dev, s, subdev_8255_mmio, regbase); in subdev_8255_mm_init()
H A D8255.c105 unsigned long regbase = subdev_8255_regbase(s); in dev_8255_detach() local
107 release_region(regbase, I8255_SIZE); in dev_8255_detach()
/linux/drivers/mtd/spi-nor/controllers/
H A Dhisi-sfc.c93 void __iomem *regbase; member
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
187 writel(reg, host->regbase + FMC_CMD); in hisi_spi_nor_op_reg()
190 writel(reg, host->regbase + FMC_DATA_NUM); in hisi_spi_nor_op_reg()
193 writel(reg, host->regbase + FMC_OP_CFG); in hisi_spi_nor_op_reg()
195 writel(0xff, host->regbase + FMC_INT_CLR); in hisi_spi_nor_op_reg()
197 writel(reg, host->regbase + FMC_OP); in hisi_spi_nor_op_reg()
237 reg = readl(host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
242 writel(reg, host->regbase + FMC_CFG); in hisi_spi_nor_dma_transfer()
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-cpugear.c21 unsigned int regbase; member
35 gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, in uniphier_clk_cpugear_set_parent()
41 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, in uniphier_clk_cpugear_set_parent()
48 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, in uniphier_clk_cpugear_set_parent()
61 gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val); in uniphier_clk_cpugear_get_parent()
96 gear->regbase = data->regbase; in uniphier_clk_register_cpugear()
/linux/drivers/clk/socfpga/
H A Dclk-gate-s10.c127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
139 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
156 socfpga_clk->bypass_reg = regbase + clks->bypass_reg; in s10_register_gate()
185 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in agilex_register_gate() argument
197 socfpga_clk->hw.reg = regbase + clks->gate_reg; in agilex_register_gate()
206 socfpga_clk->div_reg = regbase + clks->div_reg; in agilex_register_gate()
214 socfpga_clk->bypass_reg = regbase + clks->bypass_reg; in agilex_register_gate()
243 struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void __iomem *regbase) in agilex5_register_gate() argument
254 socfpga_clk->hw.reg = regbase + clks->gate_reg; in agilex5_register_gate()
[all …]
H A Dclk-periph-s10.c138 void __iomem *regbase) in n5x_register_periph() argument
151 periph_clk->hw.reg = regbase + clks->offset; in n5x_register_periph()
173 void __iomem *regbase) in s10_register_cnt_periph() argument
187 periph_clk->hw.reg = regbase + clks->offset; in s10_register_cnt_periph()
192 periph_clk->bypass_reg = regbase + clks->bypass_reg; in s10_register_cnt_periph()
219 void __iomem *regbase) in agilex5_register_cnt_periph() argument
232 periph_clk->hw.reg = regbase + clks->offset; in agilex5_register_cnt_periph()
237 periph_clk->bypass_reg = regbase + clks->bypass_reg; in agilex5_register_cnt_periph()
/linux/drivers/ufs/host/
H A Dti-j721e-ufs.c19 void __iomem *regbase; member
35 ufs->regbase = devm_platform_ioremap_resource(pdev, 0); in ti_j721e_ufs_probe()
36 if (IS_ERR(ufs->regbase)) in ti_j721e_ufs_probe()
37 return PTR_ERR(ufs->regbase); in ti_j721e_ufs_probe()
58 writel(ufs->reg, ufs->regbase + TI_UFS_SS_CTRL); in ti_j721e_ufs_probe()
89 writel(ufs->reg, ufs->regbase + TI_UFS_SS_CTRL); in ti_j721e_ufs_resume()
/linux/include/linux/comedi/
H A Dcomedi_8255.h34 unsigned long regbase);
38 unsigned long regbase) in subdev_8255_io_init() argument
45 unsigned long regbase);
/linux/include/linux/platform_data/
H A Dmv_usb.h36 int (*phy_init)(void __iomem *regbase);
37 void (*phy_deinit)(void __iomem *regbase);
/linux/drivers/pinctrl/
H A Dpinctrl-at91.c57 void __iomem *regbase; member
366 return gpio_chips[bank]->regbase; in pin_to_controller()
957 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
1420 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get_direction()
1434 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_input()
1444 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get()
1455 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set()
1467 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set_multiple()
1484 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_output()
1499 void __iomem *pio = at91_gpio->regbase; in at91_gpio_dbg_show()
[all …]
/linux/drivers/platform/x86/amd/pmf/
H A Dcore.c157 return ioread32(dev->regbase + reg_offset); in amd_pmf_reg_read()
162 iowrite32(val, dev->regbase + reg_offset); in amd_pmf_reg_write()
201 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, in amd_pmf_send_cmd()
219 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, in amd_pmf_send_cmd()
463 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMF_BASE_ADDR_OFFSET, in amd_pmf_probe()
465 if (!dev->regbase) in amd_pmf_probe()
/linux/drivers/iommu/
H A Domap-iommu.h56 void __iomem *regbase; member
256 return __raw_readl(obj->regbase + offs); in iommu_read_reg()
261 __raw_writel(val, obj->regbase + offs); in iommu_write_reg()

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