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Searched refs:reg_value (Results 1 – 25 of 81) sorted by relevance

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/linux/drivers/media/spi/
H A Dgs1662.c54 u16 reg_value; member
227 if (reg_fmt[i].reg_value == std) { in gs_status_format()
243 return reg_fmt[i].reg_value | MASK_FORCE_STD; in get_register_timings()
258 int reg_value; in gs_s_dv_timings() local
263 reg_value = get_register_timings(timings); in gs_s_dv_timings()
264 if (reg_value == 0x0) in gs_s_dv_timings()
288 u16 reg_value, i; in gs_query_dv_timings() local
302 gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, &reg_value); in gs_query_dv_timings()
303 if (reg_value) in gs_query_dv_timings()
311 gs_read_register(gs->pdev, REG_STATUS, &reg_value); in gs_query_dv_timings()
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/linux/drivers/media/dvb-frontends/cxd2880/
H A Dcxd2880_tnrdmd_dvbt_mon.c392 u16 *reg_value) in dvbt_read_snr_reg() argument
397 if (!tnr_dmd || !reg_value) in dvbt_read_snr_reg()
428 *reg_value = (rdata[0] << 8) | rdata[1]; in dvbt_read_snr_reg()
434 u32 reg_value, int *snr) in dvbt_calc_snr() argument
439 if (reg_value == 0) in dvbt_calc_snr()
442 if (reg_value > 4996) in dvbt_calc_snr()
443 reg_value = 4996; in dvbt_calc_snr()
445 *snr = intlog10(reg_value) - intlog10(5350 - reg_value); in dvbt_calc_snr()
454 u16 reg_value = 0; in cxd2880_tnrdmd_dvbt_mon_snr() local
472 ret = dvbt_read_snr_reg(tnr_dmd, &reg_value); in cxd2880_tnrdmd_dvbt_mon_snr()
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H A Dcxd2880_tnrdmd_dvbt2_mon.c1228 u16 *reg_value) in dvbt2_read_snr_reg() argument
1236 if (!tnr_dmd || !reg_value) in dvbt2_read_snr_reg()
1275 *reg_value = (data[0] << 8) | data[1]; in dvbt2_read_snr_reg()
1281 u32 reg_value, int *snr) in dvbt2_calc_snr() argument
1286 if (reg_value == 0) in dvbt2_calc_snr()
1289 if (reg_value > 10876) in dvbt2_calc_snr()
1290 reg_value = 10876; in dvbt2_calc_snr()
1292 *snr = intlog10(reg_value) - intlog10(12600 - reg_value); in dvbt2_calc_snr()
1301 u16 reg_value = 0; in cxd2880_tnrdmd_dvbt2_mon_snr() local
1319 ret = dvbt2_read_snr_reg(tnr_dmd, &reg_value); in cxd2880_tnrdmd_dvbt2_mon_snr()
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H A Dcxd2880_io.c49 const struct cxd2880_reg_value reg_value[], in cxd2880_io_write_multi_regs() argument
59 ret = io->write_reg(io, tgt, reg_value[i].addr, in cxd2880_io_write_multi_regs()
60 reg_value[i].value); in cxd2880_io_write_multi_regs()
/linux/drivers/clk/
H A Dclk-max9485.c36 u8 reg_value; member
80 u8 reg_value; member
96 drvdata->reg_value &= ~mask; in max9485_update_bits()
97 drvdata->reg_value |= value; in max9485_update_bits()
101 mask, value, drvdata->reg_value); in max9485_update_bits()
104 &drvdata->reg_value, in max9485_update_bits()
105 sizeof(drvdata->reg_value)); in max9485_update_bits()
144 entry->reg_value); in max9485_clkout_set_rate()
152 u8 val = drvdata->reg_value & MAX9485_FREQ_MASK; in max9485_clkout_recalc_rate()
156 if (val == entry->reg_value) in max9485_clkout_recalc_rate()
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H A Dclk-axi-clkgen.c509 unsigned int tech, family, speed_grade, reg_value; in axi_clkgen_setup_limits() local
511 axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, &reg_value); in axi_clkgen_setup_limits()
512 tech = ADI_AXI_INFO_FPGA_TECH(reg_value); in axi_clkgen_setup_limits()
513 family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); in axi_clkgen_setup_limits()
514 speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); in axi_clkgen_setup_limits()
529 &reg_value); in axi_clkgen_setup_limits()
530 if (ADI_CLKGEN_INFO_FPGA_VOLTAGE(reg_value) < 950) { in axi_clkgen_setup_limits()
/linux/drivers/net/phy/
H A Dopen_alliance_helpers.c33 int oa_1000bt1_get_ethtool_cable_result_code(u16 reg_value) in oa_1000bt1_get_ethtool_cable_result_code() argument
35 u8 tdr_status = FIELD_GET(OA_1000BT1_HDD_TDR_STATUS_MASK, reg_value); in oa_1000bt1_get_ethtool_cable_result_code()
36 u8 dist_val = FIELD_GET(OA_1000BT1_HDD_TDR_DISTANCE_MASK, reg_value); in oa_1000bt1_get_ethtool_cable_result_code()
68 int oa_1000bt1_get_tdr_distance(u16 reg_value) in oa_1000bt1_get_tdr_distance() argument
70 u8 dist_val = FIELD_GET(OA_1000BT1_HDD_TDR_DISTANCE_MASK, reg_value); in oa_1000bt1_get_tdr_distance()
H A Dopen_alliance_helpers.h43 int oa_1000bt1_get_ethtool_cable_result_code(u16 reg_value);
44 int oa_1000bt1_get_tdr_distance(u16 reg_value);
/linux/drivers/media/dvb-frontends/
H A Dstv6111.c32 u16 reg_value; member
533 int table_size, u16 reg_value) in table_lookup() argument
542 if (reg_value <= table[0].reg_value) { in table_lookup()
544 } else if (reg_value >= table[imax].reg_value) { in table_lookup()
549 if ((table[imin].reg_value <= reg_value) && in table_lookup()
550 (reg_value <= table[i].reg_value)) in table_lookup()
555 reg_diff = table[imax].reg_value - table[imin].reg_value; in table_lookup()
558 gain += ((s32)(reg_value - table[imin].reg_value) * in table_lookup()
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-core.c344 u32 reg_value; in cti_channel_trig_op() local
375 reg_value = direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] : in cti_channel_trig_op()
378 reg_value |= chan_bitmask; in cti_channel_trig_op()
380 reg_value &= ~chan_bitmask; in cti_channel_trig_op()
384 config->ctiinen[trigger_idx] = reg_value; in cti_channel_trig_op()
386 config->ctiouten[trigger_idx] = reg_value; in cti_channel_trig_op()
390 cti_write_single_reg(drvdata, reg_offset, reg_value); in cti_channel_trig_op()
401 u32 reg_value; in cti_channel_gate_op() local
410 reg_value = config->ctigate; in cti_channel_gate_op()
413 reg_value |= chan_bitmask; in cti_channel_gate_op()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c201 uint32_t reg_value = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
205 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
207 if (reg_value) in sdma_v4_4_query_ras_error_count_by_instance()
208 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value, in sdma_v4_4_query_ras_error_count_by_instance()
212 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
214 if (reg_value) in sdma_v4_4_query_ras_error_count_by_instance()
215 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value, in sdma_v4_4_query_ras_error_count_by_instance()
H A Dumc_v6_7.c64 uint64_t reg_value; in umc_v6_7_query_error_status_helper() local
75 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
76 if (reg_value) in umc_v6_7_query_error_status_helper()
77 dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
82 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
83 if (reg_value) in umc_v6_7_query_error_status_helper()
84 dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
89 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
90 if (reg_value) in umc_v6_7_query_error_status_helper()
91 dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
H A Dmmsch_v4_0.h80 uint32_t reg_value; member
101 uint32_t reg_value; member
119 direct_wt.reg_value = value; \
H A Dmmsch_v3_0.h68 uint32_t reg_value; member
89 uint32_t reg_value; member
107 direct_wt.reg_value = value; \
H A Dmmsch_v1_0.h73 uint32_t reg_value; member
94 uint32_t reg_value; member
103 direct_wt->reg_value = value; in mmsch_v1_0_insert_direct_wt()
/linux/drivers/misc/
H A Dxilinx_sdfec.c264 u32 reg_value; in update_config_from_hw() local
268 reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR); in update_config_from_hw()
269 xsdfec->config.order = reg_value; in update_config_from_hw()
279 reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); in update_config_from_hw()
280 xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0; in update_config_from_hw()
282 reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); in update_config_from_hw()
284 (reg_value & XSDFEC_ECC_ISR_MASK) > 0; in update_config_from_hw()
286 reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); in update_config_from_hw()
287 sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0; in update_config_from_hw()
438 u32 reg_value; in xsdfec_get_turbo() local
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/linux/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c46 u32 bits, reg_value; in sun9i_usb_phy_passby() local
56 reg_value = readl(phy->pmu); in sun9i_usb_phy_passby()
59 reg_value |= bits; in sun9i_usb_phy_passby()
61 reg_value &= ~bits; in sun9i_usb_phy_passby()
63 writel(reg_value, phy->pmu); in sun9i_usb_phy_passby()
/linux/arch/mips/include/asm/sn/sn0/
H A Dhubio.h203 u64 reg_value; member
445 u64 reg_value; member
467 u64 reg_value; member
514 u64 reg_value; member
556 u64 reg_value; member
672 u64 reg_value; member
709 u64 reg_value; member
824 u64 reg_value; member
839 #define iprb_regval reg_value
/linux/drivers/video/fbdev/via/
H A Dhw.c1014 int reg_value; in viafb_load_fetch_count_reg() local
1020 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); in viafb_load_fetch_count_reg()
1024 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); in viafb_load_fetch_count_reg()
1027 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); in viafb_load_fetch_count_reg()
1031 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); in viafb_load_fetch_count_reg()
1039 int reg_value; in viafb_load_FIFO_reg() local
1159 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); in viafb_load_FIFO_reg()
1163 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); in viafb_load_FIFO_reg()
1166 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); in viafb_load_FIFO_reg()
1173 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); in viafb_load_FIFO_reg()
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H A Dlcd.c338 int reg_value = 0; in load_lcd_scaling() local
353 reg_value = in load_lcd_scaling()
359 viafb_load_reg(reg_value, in load_lcd_scaling()
373 reg_value = in load_lcd_scaling()
380 viafb_load_reg(reg_value, in load_lcd_scaling()
385 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value); in load_lcd_scaling()
397 reg_value = in load_lcd_scaling()
403 viafb_load_reg(reg_value, in load_lcd_scaling()
417 reg_value = in load_lcd_scaling()
424 viafb_load_reg(reg_value, in load_lcd_scaling()
[all …]
/linux/sound/pci/echoaudio/
H A Dechoaudio_gml.c51 __le32 reg_value; in write_control_reg() local
62 reg_value = cpu_to_le32(value); in write_control_reg()
63 if (reg_value != chip->comm_page->control_register || force) { in write_control_reg()
66 chip->comm_page->control_register = reg_value; in write_control_reg()
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c97 static inline void sg2042_pll_ctrl_decode(unsigned int reg_value, in sg2042_pll_ctrl_decode() argument
100 ctrl->fbdiv = FIELD_GET(PLLCTRL_FBDIV_MASK, reg_value); in sg2042_pll_ctrl_decode()
101 ctrl->refdiv = FIELD_GET(PLLCTRL_REFDIV_MASK, reg_value); in sg2042_pll_ctrl_decode()
102 ctrl->postdiv1 = FIELD_GET(PLLCTRL_POSTDIV1_MASK, reg_value); in sg2042_pll_ctrl_decode()
103 ctrl->postdiv2 = FIELD_GET(PLLCTRL_POSTDIV2_MASK, reg_value); in sg2042_pll_ctrl_decode()
148 static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value, in sg2042_pll_recalc_rate() argument
154 sg2042_pll_ctrl_decode(reg_value, &ctrl_table); in sg2042_pll_recalc_rate()
/linux/drivers/hwmon/
H A Daspeed-pwm-tacho.c394 u32 reg_value = ((div_high << type_params[type].h_value) | in aspeed_set_pwm_clock_values() local
399 type_params[type].clk_ctrl_mask, reg_value); in aspeed_set_pwm_clock_values()
413 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; in aspeed_set_pwm_port_type() local
415 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; in aspeed_set_pwm_port_type()
418 pwm_port_params[pwm_port].type_mask, reg_value); in aspeed_set_pwm_port_type()
425 u32 reg_value = (rising << in aspeed_set_pwm_port_duty_rising_falling() local
427 reg_value |= (falling << in aspeed_set_pwm_port_duty_rising_falling()
432 reg_value); in aspeed_set_pwm_port_duty_rising_falling()
446 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | in aspeed_set_tacho_type_values() local
451 TYPE_CTRL_FAN_MASK, reg_value); in aspeed_set_tacho_type_values()
/linux/drivers/regulator/
H A Dmt6332-regulator.c362 u32 reg_value; in mt6332_regulator_probe() local
369 if (regmap_read(mt6332->regmap, MT6332_HWCID, &reg_value) < 0) { in mt6332_regulator_probe()
373 reg_value &= GENMASK(7, 0); in mt6332_regulator_probe()
375 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); in mt6332_regulator_probe()
384 if (reg_value == 0x10) { in mt6332_regulator_probe()
H A Dmc13892-regulator.c442 u32 reg_value; in mc13892_sw_regulator_set_voltage_sel() local
447 reg_value = selector; in mc13892_sw_regulator_set_voltage_sel()
467 reg_value -= MC13892_SWxHI_SEL_OFFSET; in mc13892_sw_regulator_set_voltage_sel()
468 reg_value |= MC13892_SWITCHERS0_SWxHI; in mc13892_sw_regulator_set_voltage_sel()
470 reg_value &= ~MC13892_SWITCHERS0_SWxHI; in mc13892_sw_regulator_set_voltage_sel()
476 mask, reg_value); in mc13892_sw_regulator_set_voltage_sel()

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